搜索资源列表
Ctl_LCD
- 采用FPGA控制LCD。程序中用了两个状态机-FPGA to control the use of LCD. Procedures with two state machine
user-interface
- User Interface的设计,包括显示DAQ,Movie,Flash,Website.状态机的设计-the code of User Interface
IOcontrol
- 输入输出控制的状态机，verilog HDL源码-Input and output control state machine, verilog HDL source
65_conditioner
- 空调系统有限状态机的硬件描述 使用VHDL语言 注释详细 想要的赶紧下载吧-Air-conditioning systems of finite state machines using VHDL hardware descr iption language Notes detail you want to download
zhuangtaiji
- 十种状态机例子（VHDL）包括米勒型和莫尔型的状态机。-Dozens of examples of state machine (VHDL), including Miller and Moore type state machine.
StateMachine
- 工作流 状态机 审批工作流 wf+Asp.net approval stateMachine-wf+Asp.net approval stateMachine
ii
- 交通灯状态机Vrilog源代码 交通灯状态机Vrilog源代码-The traffic light state machine source code Vrilog traffic lights Vrilog state machine source code
8bit_LED_scan
- 8位七段码动态扫描控制VHDL设计。动态扫描模块，延时模块，译码模块。设计采用状态机思路。-The design of scan display of 8bit-segment-LCD based on VHDL
SIP
- sip体系架构的详细讲解，包括sip的语法分析和sip的状态机-sip on a detailed architecture, including analysis of sip and sip syntax of the state machine
holidaywork
- 机器状态机。控制工作方式。用vhdl写的。很不错哦-Machine state machine. Control work. Written by vhdl. Oh well
mul4
- 分析二进制乘法中计算步骤（多少次加法，何时进行），实现一个有限状态机，执行乘法运算。-Analysis of binary multiplication in the calculation of step (adding the number of times, when it will be), the realization of a finite state machine, the implementation of multiplication.
project
- 以“一主三从”主从多机通信系统为物理模型，研究应用马尔可夫链建立仿真算法及蒙特卡洛法建立了数学模型，通过将完整的系统元件化，并对每个元件创立各自的状态转移机模型，仿真运行状态，实现了对于这一通信系统的可靠性建模评估。-" One the main three from the" master-slave multi-communication system for the physical model to study the application of Markov cha
jiAOTONGDENG
- 本实验主要模拟位于十字路口的交通灯，十字路口的交通灯分为横向和纵向两 个方向，每个方向上面的交通灯有红灯亮，黄灯亮，绿灯亮三种状态。它们之间状 态的关系如上面的表格所示。 上面各个状态是连续循环变化的，可以由状态机来实现，每两个状态之间的间 隔要在10 秒左右（实验板上面的时钟频率是50MHz）。 交通灯的三种状态用实验板上的三个LED 灯表示，两个方向一共要使用六个 LED。 -Simulation of this experiment is located at
JIJIAQI
- Quartus II工程压缩文件，是一个典型的基于FPGA的计价器工程项目，有有限状态机、50MHz分频、计数、译码、动态扫描等模块。-Quartus II project files, is a typical FPGA-based project of the meter, there are finite state machine, 50MHz frequency, counting, decoding, dynamic scanning module.
Statemachinedesigntechniques
- 老外写的编写有限状态机的书，书中提供的各种技巧，方法对大家肯定很有帮助-The preparation of a foreigner to write finite state machine of the book, the book provides a variety of techniques, methods to be helpful, I am sure you
UML_StateMachineWizardVCAddin703
- UML State Machine Wizard ,作为VC++ Addin，可依据基于UML描述的状态机生成C++代码。-UML State Machine Wizard acts as a Visual C++ Add-in, which provides a UML (Unified Modeling Language) state machine programming mechanism in portable standard C/C++ for either embedded sy
software
- 一个温度控制项目,使用ds18b20,4位动态数码管显示,还有工业键盘.程序使用状态机键盘以及时间动态扫描技术-A temperature control project
state_machine
- pci 总线控制主模式状态机，主要功能是实现批次主模式读写功能-Main Mode pci bus control state machine, the main function is to achieve the main batch mode to read and write functions
mmi
- 手机mmi状态机，包括打电话、发短信、SAT-State machine of mmi of mobilephone, it s including Call, SMS, SAT etc.
vhdl
- 通用寄存器，移位寄存器，简单状态机，直流电机控制器，-General registers, shift register, a simple state machine, DC motor controllers, etc.