搜索资源列表
fir
- 用状态机编写的FIR，verilog代码，已经经过仿真-With the state machine written in FIR, verilog code, and has passed through simulation
verilog_instance
- 20多个十分实用的verilog例子，如状态机，除法器等-More than 20 very practical verilog examples, such as state machines, divider, etc.
serial_in
- verilog 串并转换程序 状态机 有4位前导码 共转换3位 可自己修改后转换更多的串行数据位-Verilog serial signal to parallel signal transfer
moore
- mooor状态机的VHDL程序，代码，状态机，关键是分析各个状态之间的切换-mooor zhuangtaiji zhuagtaiji guanjianshi gege zhuangtai zhijian de qiehuan
CM12864
- cm12864液晶显示器的vhdl驱动代码，基于状态机的转换，实现显示功能。-descripe by the VHDL to drive the LCD cm12864,based on the FSM convertor,achieve the display function.
sci_LIN
- LIN协议的实现。用状态机实现。baudrate可调整，只能做slave。-SCI communication on 68hc9s08dz60 it is not a simple sending & receiving process, utilizes a state machine
ad_converter
- 该代码可实现FPGA对AD转换器的控制，使用的是状态机-THE CODE CAN REALIZE THAT XILINX FPGA CONTROL AD CONVERTER BY USING STATEMENT MECHIN3
RISC
- RISC(精简指令集计算机)存储程序状态机的源代码-RISC (reduced instruction set computer) stored procedures source code of the state machine
FSM
- 这是用verilog硬件描述语言编的moore状态机代码-It is compiled verilog hardware descr iption language moore state machine code
USB2_LinkPowerMangement_ECN[final]
- USB的LPM spec,详细描述了LPM状态机和ACK-LPM spec for usb
win32asmCourseDesign_a_calculator_by_webee
- Win32汇编的课程设计，一个仿xp计算器的程序。 主要是熟悉windows编程，有限状态机的设计。-Win32 compilation of curriculum design, an imitation xp calculator program. Are mainly familiar with windows programming, finite state machine design.
light_controller
- 用HDL语言编写彩灯控制程序： 用状态机实现一个循环彩灯控制器，该控制器控制红、绿、黄三个发光管循环发亮，要 求红发光管亮2秒，绿发光管亮3秒，黄发光管亮1秒。程序所用时钟的频率为1HZ。-Lantern with HDL language control program: A state machine to achieve a circular lantern controller that controls red, green, yellow three LED lights c
traffic
- 交通灯的VHDL实现，使用状态机来实现，适合初学者-VHDL implementation of traffic lights, use state machines to implement, suitable for beginners
VHDL_counter
- 这是一个采用状态机设计的增减计数器；由控制位 dir 控制计数的方向，dir=‘0’ 时减计数，dir=‘1’时增计数；清零位为Clr，Clr = ‘1’时计数器清零； 启动位为Start，Start = ‘1’计数器工作，否则计数器不工作。 -This is an increase or decrease in use of state machine design counter by the control bits control the counting dir direction,
fsm
- 嵌入式系统控制面通常的状态机实现 调用FSM_Create创建状态机 调用FSM_Add创建状态机 调用FSM_Execute进入状态机执行 通过修改宏FSM_MAX_MSG_NUM定义系统最大的状态机数目-Embedded system control surfaces typical state machine implementation
uart
- 串口FPGA实现，采用了状态机的方案 串口FPGA实现，采用了状态机的方案-FPGA UART
PS0-SVR
- ：针对发酵过程中生物参数难以实时在线测量的问题，建立了用于生物参数状态预估的 支持向量机软测量模型。考虑到该支持向量回归(SVR)模型的复杂性和冷化特征取决于其三 个参数 ，c， 能否取到最优值，采用粒子群优化(PSO)算法实现对参数 ，c， 的同时寻优。在 此基础上，以饲料用 ．甘露聚糖酶为对象，建立了基于PSO—SVR的发酵过程产物浓度状态预估 模型。发酵罐控制结果表明：该模型具有很好的学习精度和泛化能力，可实现对 ．甘露聚糖酶 产物浓度的实时在线预估。-In
qf
- QP下的框架处理源码~基于状态机的实现~ -QP under the framework of the deal with source-based state machine implementation of ~ ~ QP under the framework of the deal with source ~ based on state machine implementation of ~
qs
- QP下的侦测处理源码~基于状态机的实现~ -QP under the detection processing based on state machine source code ~ ~ QP under the realization of the detection processing source ~ based on state machine implementation ~
80x86
- QP下的例子源码~基于状态机的实现~高效学习QP技术的捷径-Examples of source code under the QP state machine based on the realization of ~ ~ and efficient technique to learn a shortcut to QP