搜索资源列表
account
- 手机话费记录，通过状态机实现不同通话类型的手机话费记录功能-Their phone records, through the state machine to achieve different types of their phone call logging
weisuijiganyixulie
- 本代码给出了伪随机感应序列的编写方法，练习熟练使用状态机-This code gives the state machine of the divider to prepare and practice skilled use of state machines
FSM
- 一种简单的状态机，本程序为初学者提供了一种编制状态机的框架。-a kind of simple FSM。
top
- 简单cpu设计 -包括内存单元，运算单元，数据及模块同步单元，状态机单元-CPU design- include memory module, alu module, synchronization module(data and block), finite state machine module
FPGA_Design_tip
- FPGA设计技巧，锁存器与寄存器区别，状态机设计，门控时钟等-Improving Performance in Complex Programmable Logic Devices (CPLDs) with the FPGA Express Software
ADC0809xianshi
- 状态机对ADC0809的7段数码显示译码器设计-State machine of the ADC0809 s 7-segment LED Display Decoder
StateMachines
- 一个状态机实例，实现了一个矿工的各种状态切换，-A state machine instance, implements a variety of state of the miners switch
example2
- 自己用vhdl写的简单状态机的例子 比较简单了-vhdl Moore
modem
- 西门子MC55IMODEM模块编程，实现短信和GPRS-TCP/IP两种通信方式，采用状态机处理。实时性更高，模块做到独立，耦合性小。值得参考-Siemens MC55IMODEM module programming, SMS, and GPRS-TCP/IP two kinds of communication, using state machine processing. Real-time high, the module to achieve independence, couple
codelock
- 用VHDL实现密码锁功能，用状态机实现，分管理员和用户两种功能，可分别修改密码，重置密码等。-codelock，VHDL，state
VHDL2
- 一个关于VHDL的moore状态机的程序，让你了解状态机的运行方法。-One on the moore state machine VHDL procedures so that you understand the operation of the state machine approach.
StatesMachineTest
- 该程序为实现一个有限状态机。 CallbackFuncManager.cpp 回调函数 StatesMachineApp.h 有限状态机-The program for the realization of a finite state machine. CallbackFuncManager.cpp callback function StatesMachineApp.h finite state machine
jtd2
- 基于VHDL状态机设计的智能交通控制灯 总体设计结构框图如图2所示，共有11个功能模块，包括控制东西方向交通灯的状态机和控制南北方向交通灯的状态机、计数器模块、键盘扫描模块、数字合成模块、三个分位模块、数码管显示模块、动态显示扫描模块。-VHDL-based state machine design of intelligent traffic control lights
bujindianji
- VHDL通过设计有限状态机实现步进电机控制源码程序-VHDL implementation through the design of finite state machine source code stepper motor control program
traffic
- 该文件包括全部的交通信号灯控制的VHDL源代码以及顶层原理图的设计，七种恰当的采用了状态机，功能完全正确而稳定。-This document includes all of the traffic lights controlled by the top-level VHDL source code, as well as schematic design, the appropriate use of the seven kinds of state machines, function en
ztj
- VHDL 状态机 FPGA编程设计源代码程序你面通通都有-VHDL State Machine Programming FPGA source code program you have them all face
divider
- 带时钟及控制的多位除法器设计，利用状态机来实现控制-multi-cycle divider design
verilog_example
- 九个verilog源码例子，包括寄存器，状态机等，含testbench-9 verilog source code examples, including registers, state machines, with testbench
ADC0809_Driver
- ADC0809的硬件语言驱动驱动 利用状态机实现-ADC0809 hardware drivers using the language-driven state machine implementation