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数字锁相环dll_code
- 通信系统中,信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program
锁相环的MATLAB的仿真程序
- 锁相环的详细仿真程序
adf4360锁相环程序
- adf4360的锁相环程序,基于单片机8051.内有说明,比较有借鉴意义。
锁相环MB1504的c语言驱动程序
- 锁相环MB1504的c语言驱动程序 51单片机控制 完整版,MB1504 PLL driver of c language SCM 51 full version
LC72131.C,锁相环电路程序
- LC72131.C,锁相环电路程序,和LA1837一起时收音机的经典搭配。,LC72131.C
Cayiwei
- GPS的matlab程序,用于对产生的ca码进行移位,用在锁相环跟踪中对ca码调增 -GPS-matlab program code used to generate the ca shifting, with the phase-locked loop tracking code on the ca be adjusted by
suoxianghuan
- 此为锁相环函数发生器 包括键盘扫描程序 频率显示程序 波形显示程序-This is the phase-locked function generators including the keyboard scanner frequency waveform display shows process procedures, etc.
PLL
- LM3236锁相环程序设计-LM3236 PLL program design
Cckk6
- 通信系统仿真原理与无线应用第六章的程序,是关于锁相环与微分方程的。-failed to translate
VHDLDPLL
- 基于VHDL 的全数字锁相环的设计,里面包含了最核心的程序。-VHDL-based all-digital phase-locked loop design, which contains the core procedures.
altpll0
- 锁相环的证实程序,可以在任何编译器中执行,但是要是TI公司的平台。-Confirmed by phase-locked loop process can be run on any compiler, but if TI' s platform。
003
- 只是一个利用MATLAB实现同步数字锁相环仿真程序-Is just a realization of synchronous digital phase-locked loop using MATLAB simulation program
PLLC
- 平方载波同步法的MATLAB实现 锁相环部分的仿真程序 结果正确 可以直接使用-PLLC.M
weitongbu
- 用数字锁相环实现位同步信号提取,包含各个模块的电路设计程序。-To achieve bit synchronization with digital phase-locked loop signal extraction, each module contains the circuit design process.
pll_sim
- 这是一个根据锁相环原理编写的MATLAB仿真程序,内有详细注释,同时附带了仿真结果图。-It is MATLAB simulation program of phase locked loop,while with the simulation results Fig.
任务四 Gardner位同步算法与锁相环联合仿真
- Gardner位同步算法与锁相环的联合仿真程序.加入了时偏和频偏,能很好地锁定时偏和频偏,得到最佳采样输出。(Gardner bit synchronization algorithm and phase-locked loop joint simulation program, adding time offset and frequency offset, can well lock the bias and frequency offset, get the best sampling o
并网逆变器的程序电流环控制并有DA以及锁相部分
- 光伏逆变锁相环,使用DSP28335,实现频率跟踪,首先采样,然后PI,然后输出(Photovoltaic inverter PLL, using DSP28335, to achieve frequency tracking, first sampling, then PI, and then output)
PLL
- verilog编写的锁相环程序。可以对照参考(Verilog prepared by the phase-locked loop program. Can control reference)
PLL(锁相环)_TEST_OK
- 通过STM32程序的编写来形成闭环锁相环,锁住波形的稳定,保持系统的稳定。(Through the preparation of STM32 program to form a closed-loop phase-locked loop, lock waveform stability, maintain the stability of the system)
锁相环bpsk qpsk qam
- matlab锁相环程序 bpsk 含i路 q路信息数据和频率相位响应曲线