搜索资源列表
pll-matlab
- 通信常用锁相环仿真－matlab格式－有简单注释。-Communications Common PLL simulation-matlab format- a simple comment.
DPLL
- 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
iPhoneUI.0.2.0
- windows mobile，.netcf 2.0下的仿iphone UI，实现滑动解锁，屏幕滑动等效果，十分流畅。-windows mobile,. netcf 2.0 under the fake iphone UI, to achieve sliding unlock, sliding and other effects of the screen is very smooth.
altpll0
- 锁相环的证实程序，可以在任何编译器中执行，但是要是TI公司的平台。-Confirmed by phase-locked loop process can be run on any compiler, but if TI' s platform。
bank
- Java版本银行家算法，运行了死锁避免与死锁检测模拟程序，可以在Eclipse上直接运行-Java version of the banker' s algorithm, run the deadlock avoid deadlock detection simulation program that can run directly on the Eclipse
003
- 只是一个利用MATLAB实现同步数字锁相环仿真程序-Is just a realization of synchronous digital phase-locked loop using MATLAB simulation program
MyLOCK
- 一个锁屏幕的程序，不再电脑旁时，防止被其他人看你的电脑资料-A lock screen program is no longer next time the computer, and prevent other people to read your computer data
weitongbu
- 关于锁相法位同步的VHDL实现，包括BLOCK图。-failed to translate
255
- 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
DPLL_verilog_a
- 用verilog语言描写设计的全数字锁相环，pDF资料-With the verilog language to describe the design of all-digital phase-locked loop, pDF information
dig_pll
- 一个简易的数字锁相环，可以产生一个与输入同频同相的输出时钟-A simple digital PLL can generate an input in phase with the same frequency output clock
danpianjidiansuo
- 单片机控制电子锁技术剖析，一个比较好的资料，大家可以下载-SCM control electronic lock technology, analysis, and a better information, you can download to see if
mypll_qpsk
- MATALAB编写的QPSK用于载波同步的锁相环，其结构为平方环-MATALAB编写的QPSK的用于载波同步的锁相环，其结构为平方环
soniclean200812161411248509
- 这是一篇关于cmos锁相环频率合成器的文章-this is an article of cmos pll
lock
- 挂机锁 帮助您在离开的时候锁定计算机 你可以查看源代码 可以更改密码-Hook locks to help you out when you lock the computer can view the source code can change the password
PLL
- 利用锁相环，比较好的实现了载波同步-PLL
PLLC
- 平方载波同步法的MATLAB实现 锁相环部分的仿真程序 结果正确 可以直接使用-PLLC.M
altpllpll
- 用VHDL语言编写的锁相环源代码，可用于配置FPGA，在FPGA中实现ＰＬＬ功能。-VHDL language with PLL source code, can be used to configure the FPGA, PLL function is implemented in the FPGA.
QPSK4_Weitongbu
- 关于定时同步的Matlab仿真代码，采用锁相环技术实现-Matlab code for Timing recovery using PLL
weitongbu
- 数字锁相环实现位同步信号的提取,含电路图，和源代码-Digital phase-locked loop to achieve bit synchronization signal extraction, including schematics, and source code