搜索资源列表
systemtest
- 本程序是操作系统课程实验的死锁的检测与解除。解除方式采用撤销进程的方法。全部用数组实现。在ubuntu(linux)下编译通过。为本人原创。每次撤销个代价最小的死锁进程,释放其所拥有的资源。 所有数据都是可以自行设置的,包括进程个数,资源种类数,各进程的代价等。-This procedure is the operating system course experiment Deadlock Detection and disarmament. The lifting of the way
PLL
- 可以实现自动锁相环功能的C源程序代码模块,-Can be achieved automatically PLL function C source code modules,
Untitled1
- 锁相环一阶环的设计的仿真。自动画出线性和非线性的仿真结果-First-order phase-locked loop design simulation. Automatically draw linear and nonlinear simulation results
MTK6226
- MTK6226解锁工具本人一直在用感觉不错-MTK6226 unlock the tools I have been feeling pretty good with
006
- 基于FPGA实现的一种新型数字锁相环-Based on the FPGA realization of a new digital PLL
loop
- 对锁相环路的仿真,二阶环的仿真与分析都可以通过这个文件来到完成-Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came
timer_trigger_adc_PLL_SUCCESS
- DSP2407定时器触发ADC,并且进行软件锁相环的实现。-DSP2407 timer to trigger ADC, and the realization of a software phase-locked loop.
newDPLLdesign
- 使用VHDL语言进行数字锁相环的设计,pdf格式,可以打开-The use of VHDL language design of digital phase-locked loop, pdf format, you can open
NewWayOfDPLLdesign
- 使用VHDL语言进行设计DPLL(数字锁相环)的相关文件-The use of VHDL language design DPLL (digital phase-locked loop) of the relevant documents
DPLL2
- 全数字锁相环电路的研制,使用的是VHDL语言 -All-digital phase-locked loop circuit development, using the VHDL language
FPGA444555443
- 基于FPGA的全数字锁相环设计,内有设计过程和设计思想-FPGA-based all-digital phase-locked loop design, with the design process and design thinking
third
- 死锁和预防;操作系统实验报告,包含源码可以运行;如果要在windows 下运行使用c软件-Deadlock and prevention operating system, experimental report, including source code can run If you want to run windows software using the c
phase_lock_vhdl
- 在VHDL下实现锁相环的源码和说明文档.通常用于分频或倍频时进行相位锁定.-To achieve phase-locked loop in the VHDL source code and documentation. Normally used when the frequency or frequency-doubling phase locked.
HTC_Touch_S1unlook_tools
- S1加强版永久解锁工具,请大家试用,不错的工具.-S1 enhanced version of the permanent unlock tool, please try, a good tool.
ic
- 电子锁终端汇编程序源程序代码高可用性 大家可以多了解下-Electronic lock assembler source code end high availability you can learn more about the next
pll
- 关于数字锁相环方面的代码,觉得还可以,或许对大家有用-the code of the pll
11112323
- 基于锁相环Top-down的建模方法在MATLAB环境下建立数字锁相环完整的仿真模型,并用SIMULINK对数字锁相环的仿真模型进行仿真。 -Top-down phase-locked loop based on the modeling method in MATLAB environment DPLL set up a complete simulation model, and use of digital phase-locked loop SIMULINK simulation mod
PcLock
- 屏幕挂机锁程序,具有一定的参考价值!暂无发现BUG!-pclock
FrequencySynthesisbyPhaseLock
- 书籍频综和锁相环的Matlab源代码,对频综和锁相环的设计很有帮助;-Books PLL Frequency Synthesizer and the Matlab source code for PLL Frequency Synthesizer Design and helpful
pll
- 实现同步时采用锁相环,锁相环实现的原理,及源代码,-Implementation of the principle of phase-locked loop, and the source code,