搜索资源列表
divider
- 基于FPGa的32为除法器，从别的地方搞来的，给大家共享以下，算是做贡献。-Divider based on the FPGA 32, to engage in from somewhere else, to share the following to be considered to contribute to.
ISE-graphics
- 3D图形，单精度浮点乘法器，单精度浮点除法器，单精度浮点乘累加器-3D graphics,single float pointing multiplier, single float pointing divider,single float pointing MAC
divider
- 除法器设计，有详细的步骤-Design of divider, detailed steps
immediate_float_divide_module
- 单精度浮点数除法器。用组合逻辑实现。高精度。-Single-precision floating point divider.
Divider
- 一个除法器的FPGA代码设计 Divider-fpga Divider
divider
- verilog很省资源的除法器，（用减法，需要时钟）验证通过-Province resources division, verified by
divider
- VERILOG编写的24位除法器代码核，是FPGA或者ASIC设计中的一核心计算模块。-VERILOG written 24 divider code nuclear FPGA or ASIC design in a core module.
Div
- 非常好用的小数除法器，verilog开发的。quartusii下综合通过-Very easy to use fractional divider, verilog developed. quartusii under comprehensive by
FPGA_Divider
- FPGA实现除法器的功能，并行逻辑计算，输出结果为商和余数。适用于FPGA内部无IP核等的低端FPGA器件上。-Function of Divider based on FPGA logic,output result includes the quotient and remainder. This function is applied to the low-end FPGA devices
Verilog_divid
- vhdl语言描述传统除法器，传统乘法器的改进，从原理到实现的传统除法器-vhdl language to describe the traditional divider, the improvement of traditional multiplier principle to achieve the traditional divider
div1
- Verilog HDL语言16位除法器，已通过测试-Verilog HDL 16 division
divider
- 除法器，经过验证,性能优良，值得下载，应该是定点除法的-divider,it is verified and good performance
74845002vhd_divider
- 除法器，用于求余用算，流水线性运算，， -Divider, for the remainder used to count
divider
- verilog的除法器 有多重方法 很适合初级者阅读-verilog divider multiple method is very suitable for beginners to read
实例模块
- 各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench
divider
- 用verilog实现一个被除数位8位、除数为4位的高效除法器-Verilog to achieve a dividend of 8, division by four efficient divider
chufa
- 用VHDL设计的四位除法器，可以实现四位二进制数的除法操作-Four divider with VHDL design, you can achieve the four binary division operation
divider
- 基于移位相减运算的除法器设计，完整的设计工程文件在divider文件夹下-Based on the shift subtraction divider design, complete design project file divider file folder
VHDL_book2
- add4a：4位加法器的设计 add8a：8位加法器的设计 subtract：4位减法器的设计 addsub： 4位加法器/减法器的设计 shift4：移位寄存器的设计 mult4：乘法器设计 div8：除法器设计 alu4：算术逻辑单元ALU设计-add4a: 4-bit adder design add8a: 8 bit adder design subtract: 4-bit subtraction Design addsub: 4-bit ad
div16d8
- 16位除以8位除法器，Verilog HDL语言-16 divided by 8 divider, Verilog HDL language