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数据选择器vhd源代码
- 数据选择器，半加器，3-8译码器vhd源代码。是最近学校的实验内容。我要成会员，所以都发上来供大家参考。-data selection, half-adder ,3-8 decoder vhd source code. Recent experimental schools content. I want to become members and therefore has made onto for reference.
3-8
- 3-8译码器学校课程设计上载以大家共享，如有不足请多指教-3-8 decoder school curriculum designed to contain share, if insufficient please enlighten
3-8译码器
- vhdl的3-8译码器-instantiate the 3-8 decoder
3-8
- 本文件是利用verilog实现的3-8译码器
VHDL语言实现3—8译码器
- 应用VHDL语言编写的3—8译码器，简单易懂
FPGA简易3-8译码器
- QUARTUS II实现的简易3 8译码器
3-8
- 3-8译码器，可以讲三位二进制输入转换为8中取1的输出信号-3-8 decoder, you can talk about the three binary input is converted to 8 of the output signal from 1
3-8-encoder-design
- 通过应用QUARTUSII开发软件对3—8译码器进行设计，给出运行程序和结果-Development through the application of QUARTUSII 3-8 decoder software for design, operational procedures and results are given
74HC138 译码器实验
- 1 3 8 译码器实验,这个是单片机51系列写的- 138 decode use for 51 mcu
3-8
- 8实验八：利用语言实现3-8译码器、8实验八：利用语言实现3-8译码器-8 Experiment 8: the use of language to achieve 3-8 decoder 8 Experiment 8: language 3-8 decoder
3-8
- 3—8译码器,在fpga上实现3,8译码的功能-decoder 3 8
3-8
- 基于verilog的3—8译码器，设计简单，程序清晰易懂-Based verilog 3-8 decoder design is simple, clear and understandable procedures
3-8-assign
- 此程序采用assign语句实现3-8译码器功能，仿真波形正确。-This program uses the assign statement to realize 3-8 decoder function, simulation waveform is right.
3-8-decoder
- 用Labview2014编写的一个3-8译码器-A 3-8 decoder program with labview 2014
3-8decorder-bh
- 学生练习3—8译码器行为级 verilog 代码(Students practice the 3 - 8 decoder behavioral level Verilog code)
3 8
- 用VHDL多种方法实现3-8译码器,元件例化(use VHDL realize 3-8decoder)
decoder3_8
- 输入信号为3位的in，输出信号为8位的out，实现3-8译码器的功能(The input of 3 bits, 2 hexadecimal number translated into 10 hexadecimal output)
ENCODER38
- 基于fpga的vhdl的3-8译码器程序。可以有效译码(3 8 decoder base on vhdl.)
3-8译码器VHDL描述
- 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4；利用XIlinX编程，使用VHDL语言来描述组合逻辑器件3-8译码器(In the FPGA:Spartan-3E development board series, XC3S500E, FGT320, -4 package: speed; the use of XIlinX programming, using VHDL language to describe the combination
VHDL实现3-8译码器
- VHDL实现3-8译码器,使用VHDL硬件描述语言，实现简单的3-8译码器等功能。