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fifo
- 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
ADPCM_audio_codec
- ADPCM语音编解码电路设计及FPGA实现。利用FPGA进行ADPCM编码与解码。-ADPCM voice codec circuit design and FPGA realization. FPGA for use ADPCM encoding and decoding.
ADPCM
- APPCM算法和AD/DA芯片驱动在CPLD中的实现，已在实际硬件中测试OK，quartus2环境-APPCM algorithm and AD/DA chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment
fifo
- 同步FIFO 创建一个256x8大小的同步FIFO，并通过串口发送数据初始化FIFO，FPGA内部读取FIFO的数据通过窗口发送到PC-FIFO