axi 总线 设计 和 仿真， 可以在设计中直接运动， 提供完整源代码和仿真文件， 用vhdl 语言实现。-axi bus design and simulation, you can directly exercise in design, providing full source code and simulation files, using vhdl language.

axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)

使用 VIVADO 工具简单高效的创建AXI接口的ip，支持 AXI4LITE, AXI4-STREAM, AXI4-FULL 可方便的实现IP间互联(Use VIVADO tool to create AXI interface IP simply and efficiently, and support AXI4LITE, AXI4-STREAM, AXI4-FULL to facilitate IP interconnection.)