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AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
PWM_modem
- 8bit PWM encoder and decoder, the zip includes PWM timing and both decoding and encoding modules. The system will run perfectly on any CPLD or FPGA. Documentation regarding the design is also included.
PseudoHC11_MCU
- This extensive proyect turns an FPGA or CPLD into an HC11 simulation. It takes in various opcodes and performs several 8bit operations. The package includes an ALU, UART, RAM module, LCD display and 7 segments as well.-This extensive proyect turns an
Reflex
- This simple program tests the reflex of a person. It will randomly start a timer and after some seconds the person will be told to press a certain button. The CPLD or FPGA will know with a resolution of 1mS the time elapsed time between the command a
qiduanxianshiyima
- 利用译码程序在FPGA/CPLD中实现16进制数的译码显示.通过EDA原理图设计方法利用prim库中7448芯片进行7段译码显示-Using decode program FPGA/CPLD realized in hexadecimal number decoding display. Through the EDA principle diagram design method using the prim library 7448 chips for 7 period of decodin
CRC
- 在CPLD 或者ＦＰＧＡ中实现CRC,可以查找表方式或根据原理去实现-CPLD or FPGA CRC can lookup table according to the principle
newdecode
- 密码锁，大学数字eda课程顺序锁的源代码，有2位或者4位的顺序锁，可以在fpga或者cpld上实现 -Password lock, digital eda course the order of the source code of the locks, the order of two or four locks, and can be implemented on the fpga or cpld
num09211870
- 北邮大学VHDL课程的结课题代码，一种基于fpga或者cpld实现的拔河机器代码-BUPT Results of VHDL course subject code, based on fpga or cpld tug of war machine code
FPGAkeshe.doc
- 基于FPGA/CPLD的以QUARTUS2 的能够实现交通灯的显示与控制-enable the lingting traffic display
7845_VGA
- 此文档是一个DE0的关于VGA的例程，用于FPGA/CPLD开发。-This document is a DE0 VGA routines, to FPGA/CPLD Development .
VHDL-CODE
- 书籍源代码_基于Altera FPGA/CPLD的电子系统设计及工程实践 -Books source code _ of Altera FPGA/CPLD-based electronic system design and engineering practice
11111
- 1、用FPGA/CPLD实现HS162字符液晶显示。 2、分析相应的功能要求，分析CPLD与字符液晶HS162的接口典型电路。 3、利用状态机的设计方法，通过指令编程实现对HS162-4液晶模块的读/写操作，以及屏幕和光标的操作。 4、编写模块的Verilog HDL语言的设计程序。 5、在Quartus II软件或其他EDA软件上完成设计和仿真。 -This design of a CPLD-based controls HS162 to achieve character
FHT_example
- 面积和速度的互换是FPGA/CPLD设计的一个重要思想。乒乓操作、串并转换-The balance between area and speed is a important idea in the design of FPGA/CPLD. Ping-pong operation、the conversion between series and parellel
xapp693
- 通过CPLD配置xilinx FPGA及程序版本管理的参考设计。-Reference design of XAPP693.
Xilinx-Configuraon-Reference-
- 本应用笔记讨论的是Xilinx 的复杂可编程器件（CPLD）、现场可编程门阵列（FPGA）和PROM系列的配置和编程选项。它示意了每个系列的最常用的一些配置方法。-This application note of the discussion is the complex programmable device Xilinx (CPLD), field programmable gates array (FPGA) and PROM series of configuration and pro
HOW-TO-USE-XILINX-ROMS
- 如何更好设计应用Xilinx FPGA/CPLD的ROM-How to better design application of the Xilinx FPGA/CPLD ROM
Choosing-signal-generator
- 基于FPGA的模拟信号源设计（中英文翻译） CPLD 信号发生器 频率捷变 无线电-FPGA signal generator frequency-agile
qi-duan-yi-ma-qi
- 七段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是2进制的，所以输出表达都是16进制的，为了满足16进制数的译码显示，最方便的方法就是利用译码程序在FPGA\CPLD中来实现。本实验作为7段译码器，输出信号LED7S的7位分别是g、f、e、d、c、b、a，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别为1、1、0、1、1、1、0、1。接有高电平段发亮，于
decode_38
- FPGA/CPLD平台，很好用的3-8译码器源程序。-FPGA/CPLD platforms, the very well with the 3-8 decoder source.
lcd_triangle
- LCD液晶屏显示。FPGA和CPLD都能用。显示一个三角波。-LCD display. FPGA and CPLD can be used. Display a triangular wave.