搜索资源列表
simulator
- 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is
ddr2_device_operation_timing_diagram_may_07_1
- DDR2时序规范，DDR· DDR2时序规范，DDR·-DDR2 timing norms, DDR DDR2 timing norms, DDR
c_xapp851
- 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes
ddr_verilog_xilinx
- xilinx公司原版的DDR时序控制源码.-xilinx' s original source code of the DDR timing control.
DDR_SDRAM_design_and_conclusion
- DDR SDRAM总结文档，描述了DDR IP的设计挑战，接口时序，模块设计原则，调试技巧及应用指南-DDR SDRAM summary document describing the design challenge of DDR IP, interface timing, modular design principles, debugging skills and Application Guide
SDRAM_DDR_DDR-II_Rambus_DRAM
- 内存的原理和时序(SDRAM、DDR、DDR-Ⅱ、Rambus_DRAM)-The principle and the timing of the memory (SDRAM, DDR, DDR-II, Rambus_DRAM)
jedec_ddr_data
- DDR addressing details and AC timing parameters from JEDEC specs.
jedec_ddr_data
- DDR addressing details and AC timing parameters JEDEC specs. -DDR addressing details and AC timing parameters JEDEC specs.
hasannorm
- describe synopsis ommonly use double data rate (DDR) memory IP to boost memory bandwidth, but they often struggle to meet timing budgets for these high-speed interfaces. Designers who incorporate DDR IP into systems-on-chip (SoCs) and use externa
DDR的原理和时序
- 嵌入式DDR时序方面的书籍，对调试时序有帮助(The principle and timing.Rar of DDR)