16×4bit的FIFO设计,VHDL语言编的的，能在ISE上仿真出来结果。

it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a

This code is a FIFO memory vhdl developed in ISE Software

异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo