搜索资源列表
fpga-LCD1602
- 本程序是用verilog开发的实现LCD1602的代码(This procedure is developed using Verilog, LCD1602 code.)
szmb
- 用VHDL语言基于ISE，在XILINX FPGA开发板上编写的数字秒表程序(Using VHDL language, based on ISE, in the XILINX FPGA development board prepared by the digital stopwatch program)
FPGA应用开发入门与典型实例_源代码
- FPGA应用开发入门与典型实例源代码，非常适合刚开始学习fpga的学生(FPGA application development portal and typical instance source code)
sys
- ARM m4 FPGA顶层模块，用于相应的FPGA开发(ARM M4 FPGA top-level module, for the corresponding FPGA development)
ahb2apb
- ARM m4 FPGA开发模块，用于 ahb2apb的模块接口(ARM M4 FPGA development module for ahb2apb module interface)
spi
- ARM m4 FPGA开发模块，用于spi接口模块开发(ARM M4 FPGA development module, used for SPI interface module development)
timer
- ARM m4 FPGA开发模块，用于timer模块的开发(ARM M4 FPGA development module, used for the development of timer module)
uart
- ARM m4 FPGA开发模块，用于uart接口的模块开发(ARM M4 FPGA development module for UART interface module development)
至简设计法--万年历
- 万年历 工程说明 在FPGA设计中，数字万年历属于小规模集成电路。从原理上来讲，是典型的数字电路，包括组合逻辑电路和时序电路。基于FPGA开发除设计简便、开发成本低、电路简洁等，更具备功能设计灵活方面的优势。 案例补充说明 万年历是记录一定时间范围内的年历，其名称只是一种象征，表示时间跨度大。由于其功能非常常用，且极为方便人们查询使用，因此广泛应用于钟表、历书出版物、电子产品、电脑软件和手机应用等行业中。(Perpetual calendar Engineering descr iption
stm32开发板FSMC读写FPGA
- STM32通过fsmc总线与FPGA通信(stm32 communication with FPGA by FSMC bus)
A4_Uart_Top
- 提供一般FPGA开发板的Uart通讯协议(Provides the Uart communication protocol for the general FPGA development board)
Verilog HDL logic programming
- FPGA常用逻辑的Verilog HDL语言实现，实用的FPGA开发参考资料。(Verilog HDL programming methods of common FPGA logic)
MiS603 FPGA开发教程V1.4(HDL)
- MIZ MIS603资料，FPGA ,VERLOG 语言，介绍一些接口的驱动设计(MIZ MIS603 data, FPGA, VERLOG language, introduced some of the interface driver design)
PS2鼠标VGA画笔
- 鼠标连接到FPGA开发板PS2, 通过VGA显示鼠标移到。(The mouse is connected to the FPGA development board PS2, and the mouse is moved through the VGA.)
Verilog_Beep
- 用Verilog语言，quartus软件，实现fpga开发板上按dou lai mi fa等7个音实现按键弹钢琴(Verilog language, quartus software, to achieve fpga development board by dou lai mi fa 7 sound to achieve the key to play the piano)
13_CMOS_OV7725_Gray_Mean_Filter
- 基于FPGA开发的均值滤波程序，效率很高，非常有用(Based on FPGA development of the mean filter program)
Miz702 ZYNQ开发教程（FPGA)
- 基于ZYNQ的FPGA教程，详细阐述了ZYNQ系列FPGA的开发过程(Based on the FPGA tutorial zynq, elaborated in detail the zynq series FPGA development process)
test_sd8_ychdj1280000
- fpga 开发，主要是针对nios核的一些开发，希望大家能相互的交流交流。(FPGA development, mainly for the development of some of the NIOS kernel, I hope we can exchange and exchange with each other)
基于Quartus-II-的FPGACPLD开发
- 基于Quartus-II-的FPGACPLD开发(Development of FPGACPLD based on Quartus-II)
dr6—ise-F
- 用FPGA开发板的按键作为电子表的时间初值设置控制信号，数码管当前时间值输出。用按键选择分别输出：分、秒、1/10秒。(With FPGA development board button, as the time value of the electronic table, set the control signal, digital tube current time value output. Select output by buttons: minutes, seconds, and