搜索资源列表
cortexm1 VHDL 源码
- 基于ACTEL公司最新的FPGA 开发板 fusion系列的 处理器CORTEXM1的顶层文件
成功移植到Xilinx Virtex6下的LWIP源码
- 成功移植于xilinx virtex6下面的LWIP协议栈,成功实现1G以太网TCP/UDP,UDP下实际测试数据传输率可打到900Mbps以上
CJQ-V1.0-fpga
- 主要实现采集电网信号的功能,源码包括控制AD7606进行AD转换,其次实现FT3数据的传输,包括转为曼彻斯特编码-Collecting grid signal to achieve the main function, including control of AD7606 source for AD conversion, followed by the realization of FT3 data transmission, including to Manchester encoding
AMI-BIOS-sourcecode.zip
- AMI 主板的BIOS源码,虽然老,但是对于做操作系统的朋友还是有借鉴价值的,还有做虚拟机开发的也很需要。,AMI motherboard BIOS source code, even though the old, but the operating system so there is still drawing on the value of a friend are also doing virtual machine to have much need for development.
DDR_SDRAM.rar
- DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA,DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
vga.rar
- 最全的FPGA VGA方面的资料及源码. VGA IPcore的Verilog代码 VGA接口设计实例及测试程序 VGA接口设计实例及测试程序(源码) VGA显示源码,FPGA VGA most comprehensive information and source code. VGA IPcore the Verilog code VGA interface design and testing procedures VGA interface design and testing p
FFT_16.rar
- FFT快速傅立叶变换-verilog,基于verilog的FFT源码,QuartusII上仿真通过,FFT Fast Fourier Transform-verilog, the FFT-based verilog source, QuartusII through the simulation
dacconf.rar
- 通信中常用的AD9857芯片的FPGA配置源码VERILOG实现,Communications commonly used in the AD9857 chip FPGA realization of VERILOG source configuration
Xinlinx_Spartan3E500_RevD_10.1
- 这个是我使用xilinx EDK 10.1建立的用语移植petalogic的uclinux发行版本petalinux-v0.4-rc2的Platform工程,开发板使用的是Spartan3E Starter Kit。在这个基础上可以直接裁剪内核后在FPGA中运行uclinux。内核源码可以到developer.petalogix.com下载。,This is a xilinx EDK 10.1, I use the term established by the uclinux transpla
FPGA
- OV7670摄像头上位机软件配合使用的FPGA程序源码(整套系统需要上位机软件,CY7C68013程序,FPGA程序)-The OV7670 camera head machine software with the use of FPGA program source code (the entire system requires the host computer software, CY7C68013 program, FPGA program)
DAC0832
- 关于FPGA控制dac0832的VHDL源码-With regard to the VHDL source FPGA control dac0832
yinpin
- 这是全国一等奖作品音频信号分析仪的FPGA源码,该设计采用FFT的设计方法,其中FFT利用IPcore,采用的是burst流型的,减少了计算量,保证了频谱更新及时。-signala analysis by FPGA,by FFT
8.4ADC0809
- FPGA中用VHDL编写的AD0809的转换接口电路及程序源码-FPGA using VHDL prepared AD0809 conversion interface circuit and program source code
uart_lcd
- fpga通过串口输入字符显示在1602lcd上,编译仿真通过,完整源码-Through the serial input character is displayed in the 1602lcd
vga_control
- vga 控制器的verilog 源码 ,fpga上可实现图片的显示-vga controller Verilog source code, fpga achievable picture display
fpga_ads8364
- fpga控制ti的多通道高精度ad芯片ads8364的verilog源码-fpga multi-channel high-precision control ti ad-chip ads8364 the verilog source code
opencore
- 基于FPGA的视觉采集系统的实现,verilog源码-FPGA-based visual collection system, verilog source
SPI
- Verilog SPI 源码(来自网络)-Verilog SPI
soure
- 用VHDL开发NES程序。这里是其配套的详细的VHDL语言源码。可用quartus进行验证。-NES with the VHDL development process. Here is the complete source of detailed VHDL language. Quartus available for verification.
CJQ-V1.0-fpga
- 主要实现采集电网信号的功能,源码包括控制AD7606进行AD转换,其次实现FT3数据的传输,包括转为曼彻斯特编码-Collecting grid signal to achieve the main function, including control of AD7606 source for AD conversion, followed by the realization of FT3 data transmission, including to Manchester encoding