搜索资源列表
basketball24
- 基于FPGA的篮球24秒计时器，开发环境为MAXPLUS-24 second timer in the FPGA-based basketball,Development environment for MAXPLUS
miaobiao
- 它具有计时功能。此秒表有两个按键（reset， start）按下reset键后，秒表清零，按下start键后，开始计时，再次按下start键后， 暂停计时，秒表显示内容闪烁。 用FPGA开发板上的两个七段数码管显示时间（以秒为单位），计时由0 到 59 循环。-It has a timer function. This stopwatch has two buttons (reset, start) reset button is pressed, the stopwatch is clear
nios-II
- NiosII范例，包括了DMA控制，串口通信，定时器中断，以及NIOS的部分范例，对于FPGA内核的开发很有帮助。-NiosII example, including the DMA control, serial communication, timer interrupt, as well as some examples of NIOS, development will be helpful for the FPGA core.
nios_ii-irq
- ALTERA FPGA 构建nios ii CPU ——中断法定时器 本例子教你学会FPGA NIOS中断，熟悉中断，逐步深入。-ALTERA FPGA build nios ii CPU- to interrupt method timer this example teach you to learn to FPGA NIOS interrupt, familiar interrupt gradually deepened.
dianziqin
- FPGA课程中，实验四电子琴设计代码。它可实现分频计时器，顶层调用等功能。-FPGA courses, experimental four flower design code. It can achieve divide timer, top calls and other functions.
nixietubenew
- FPGA片上运动计时器实现，使用数码管显示计时，包含暂停与重置-Movement on the FPGA chip timer implementation, use digital display timing, including pause and reset
quartus_works_first
- 基于verilog语言的，FPGA程序，实现可暂停的计时器与数码管显示功能，计时范围0~99秒，精度0.01秒，在EP1C3T100C8上亲测通过-Based verilog language, FPGA program implementation can pause the timer with digital display function, time range from 0 to 99 seconds, precision 0.01 seconds, measured by the
NIOS_DIG
- 基于FPGA软核系统，通过nios编程使开发板数码管定时计数-FPGA-based soft-core systems through programmed to nios development board digital timer count
24
- 基于6M晶振FPGA的篮球24秒计时器verilog HDL代码，附testbench-Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
pika_wdt
- PIKA FPGA based Watchdog Timer.
time
- FPGA做的电子钟，通过定时器实现。用vhdl做的led ip核，软件实现控制显示-FPGA do electronic bell, by timer implementation. Led ip vhdl do with nuclear, software control display
led
- FPGA做的led流水灯，quartus搭的nios，计时器每隔一秒led点亮一次，四个流水灯循环显示，适合新手学习-FPGA do led light water, quartus ride nios, timer once every second led lights, four light water cycle, for beginners to learn
test6_timer
- 这是有Quartus II和Nios II共同协作完成的基于FPGA的异步电机矢量控制系统，里面包含定时器，LCD显示，温度检测等内容-This is the Quartus II and Nios II work together to complete induction motor vector control system based on FPGA, contains a timer, LCD display, temperature detection, etc
TIMER_test
- DSP6713的定时器测试程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 timer test program, including the FPGA interface program, DSP and FPGA to work together.
9_timer
- fpga的nios timer程序，可快速了解fpga nios核的配置方法-fpga' s nios timer program, you can quickly learn how to configure fpga nios nucleus
led_demo
- fpga初始化，实现led流水灯实验，数码管计时，以及开发板各模块初始化-fpga initialize realize led light water experiments, digital timer, as well as the board of each module initialization
syscall_table
- PIKA FPGA based Watchdog Timer.
Gameone
- 此秒表有两个按键（reset， start）按下reset键后，秒表清零，按下start键后，开始计时， 再次按下start键后， 停止计时， 用FPGA开发板上的两个七段数码管显示时间（以秒为单位），计时由0 到 59 循环。 高级要求（可选）：实现基本要求的前提下，增加一个按键（select），用于轮流切换两个七段数码管分别显示百分之一秒，秒，分钟。 规格说明： 1.通过按下reset键（异步复位），将秒表清零，准备计时，等检测到start键按下并松开后，开始计时 。如果再次检测
zx3016_clock
- 24/12小时计时器，能够转换24/12小时制，能够显示星期、年月日、以及阴历等，能够在fpga开发板上运行-24/12 hour timer, 24/12 hour format can be converted, it will show the week, the date, and the lunar calendar, etc., can run in the fpga development board
sos_module
- 用FPGA实现sos摩尔密码，即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”，“画”和“间隔”。而 control_module.v 是一个简单的定时触发器，每一段时间都会使能sos_module.v。-Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password,