搜索资源列表
FPGA
- FPGA串口通信 Verilog -FPGA UART uartFPGA UART
reaction-time_FPGA_Verilog
- 基于FPGA的反应时间测试机——verilog HDL-Based on the reaction time test machine in the FPGA- Verilog the HDL
Verilog-HDL-digital-system-design
- Verilog HDL数字系统设计教程,其中对Verilog HDL语言的语法，FPGA的结构及其应用作了详细的讲解-Verilog HDL digital system design introduces the Verilog HDL language and the FPGA function including syntax ,FPGA frame and application and so on
uart-of-fpga
- FPGA实现UART通信程序，verilog hdl语言实现的，好用-UART of FPGA
FPGA--Driving-AT070TN92
- FPGA驱动群创数字屏液晶AT070TN92显示verilog代码-Driven by the FPGA Innolux digital screen display LCD AT070TN92, verilog code
digital-signal-processing-with--fpga
- 数字信号处理用FPGA实现，其中包含常见的FFT，滤波器，自相关等用VHDL和Verilog语言实现的-digital signal processing with fpga
matrix-keyboard-
- 矩阵键盘控制的FPGA，verilog语言实现，包括rtl，ucf,以及testbench的详尽代码-Exhaustive code matrix keyboard control FPGA, Verilog language, including the rtl, ucf, and testbench
verilog
- AD0809电压采集的芯片资料关于FPGA资料的一些说明
ecp3pSerDes_Reset__Code
- ecp3 fpga verilog 复位程序 用来复位FPGA内部serdes -ecp3 fpga verilog reset procedure
FPGA-development--and-VHDL--based
- FPGA开发流程简介与Verilog HDL语言基础-FPGA development process and VHDL language based
1602-drive--fpga
- 基于fpga的1602液晶显示驱动 verilog hdl-1602 drive based on fpga
FPGA-1602
- 利用verilog语言实现LCD1602的驱动并显示-Use verilog language implementation LCD1602 driver and display.
mulx
- FPGA verilog乘法器 设计 用FPGA中DSP模块实现-FPGA verilog mulx
verilog--uart
- verilog实现uart功能的FPGA应用，适用于Cyclone 2系列-verilog uart function of FPGA applications in the Cyclone Series
verilog--sram
- ram的fpga应用，用verilog语言实现，适用于cyclone 2系列-ram the fpga application verilog language applicable to cyclone 2
lms
- 文件中为lms算法的ise工程，其中包含了lms算法的fpga实现的verilog程序以及testbench，很好的在FPGA上实现了lms算法，还有一些调试程序的总结-Ise project file for lms algorithm, which contains the lms algorithm fpga verilog program to achieve and testbench good lms algorithm implemented on FPGA debugger su
Verilog-SPI
- 用FPGA实现SPI通讯，使用VerilogHDL语言编写，附相对应的MCU端时钟配置注意事项-Using FPGA implements SPI communication, Code use VerilogHDL language, attached corresponding to the MCU side clock configuration Note
fpga-uart
- 基于DE2开发板的串口通信程序，使用Verilog HDL语言，-Serial communication program based on the DE2 board, using the Verilog HDL language
FPGA-kaifang
- fpga 开方，用verilog语言实现，完成开方运算，方便好用-fpga kaifang，verilog langlange
FPGA
- vga的图像动态显示，用verilog编写，运行成功。对初学者很有帮助。-vga image dynamic, with verilog to write and run successfully. Useful for beginners.