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用FPGA实现DDS信号发生及用MODELSIM仿真
- 该工程是用verilog编写,FPGA内部产生ROM及ADD加法器。ROM中存正弦波信号。文件夹中还包含modelsim仿真。
DDS.rar
- FPGA控制AD9854的源文件,verilog,附有简单文档。,FPGA to control the AD9854 source file, verilog, with a simple document.
dds
- verilog 硬件语言实现DDS,使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
dds
- 基于FPGA的DDS设计,本程序采用verilog HDL语言编写,使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
DDS
- DDS文件夹内的程序,完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square
FPGA-DDS
- 在FPGA内,以查表方式实现频率直接合成器(DDS)功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
dds-design
- fpga实现dds,实现任意波形输出信,设计代码verilog-dds fpga realization
AM
- FPGA内AM调制工程。内带调制波、载波生成。关键词:FPGA verilog AM DDS-AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS
dds
- 关于FPGA中DDS核参数设置的资料,英文版的XILINX资料-DDS on the FPGA in the data set of nuclear parameters, the English version of XILINX information
dds
- DDS文件夹内的程序,完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序-ewfreytrgrwf reggwrter rgterthhrgdfs rgdgf egrthg rgreaf rtgerf srfefsf frafgsf frghrsrgwgt
DDS
- 基于Verilog的dds设计,已经经过调试,可直接使用-Dds of Verilog-based design, has been testing can be used directly
DDSVerilog
- DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation
DDS
- 同时用verilog 语言编写dds原代码用于生成正余弦波,并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
DDS__FPGA
- 基于FPGA的DDS信号发生器设计,包含Quartus 的工程,打开即可使用,Verilog 语言编写!-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容
DDS-in-Verilog
- Verilog编写基于FPGA的DDS实现,内含源代码,希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
dds(1)
- 基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
DDS
- 基于FPGA的DDS正弦信号设计,文件中有源代码(Design of DDS based on FPGA)
ex_DDS
- 基于Verilog语言实现DDS(数字频率合成器)的设计,有完整的工程设计代码和仿真脚本(Verilog language based on DDS (digital frequency synthesizer) design, there is a complete engineering design code and simulation scr ipts)
DDS
- 用verilog语言,在fpga上实现dds信号发生器,并在vga上显示出来(Verilog realizes DDS Signal Generator)
DDS
- DDS FPGA Verilog vhdl