搜索资源列表
FENPIN48
- FPGA分频器，利用计数器计数，将外部晶振的48MHZ时钟分频为1MHZ-48M frequency division 1M frequency divider
VHDL-Code-and-TestBench-Code
- 实现了三个功能电路的程序：时钟分频电路；移位寄存器；序列检测器。-Including three parts:frequency divider shifting register sequential detector
sin
- 用VHDL语言编写实现以下功能：用PLL，复位器，分频器，同步时钟，计数器来产生正弦波，再在其上加扰，用FIR滤波器进行滤波整形，最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter sh
fenpin
- 通用整数分频器，可以分频占空比为1:1，也可以为任意占空比-General integer frequency divider, can divide frequency and duty ratio of 1:1, also can be for any duty ratio
diviseurFrquence50MhzTo1hz
- this file about frequency divider 50 MHz to 1 Hz used in 7-segment display
divider-achieved-by-verilog
- 该代码用Verilog语言实现了分频功能，主要实现对输入时钟的54分频，已通过仿真验证。-The code in Verilog realize the crossover functions, the main achievement of the input clock frequency of 54 minutes, has been verified by simulation.
4.5fenpingqi
- 基于FPGA的关于verilog语言的4.5分频器及其仿真波形图-FPGA based on verilog language frequency divider and its simulation waveform in figure 4.5
fenpinqi
- 数字分频器，包括分频器单位冲击响应及幅频响应-Digital frequency divider, including frequency divider unit impulse response and amplitude frequency response
UD_DIVDER
- 定制化分频器的verilog源代码，分频器变量已参数化，好用-Customized divider verilog source code, variable frequency divider parameterized, easy to use
half_integer
- 数控分频器：以2.5分频为例的半整数分频器-half-integer frequency divider
divider8
- 使用硬件描述语言设计8分频器，并将结果通过七段数码管显示-The hardware descr iption language is used to design the 8-frequency divider, and the result is displayed by 7-segment LED
fenpin5
- 五分频器的VHDL语言设计，改变相关参数，可得到其他分频器，便于学习VHDL语言-Five frequency divider VHDL language design, change the relevant parameters, you can get other dividers, easy to learn VHDL language
Example5
- 数控分频器设计 数控分频器的功能就是当输入端给定不同的输入数据时， 分频器对输入时钟 信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器来设计 完成的，方法是将计数溢出位与预置数装载信号相接得到-NC NC divider divider design feature is that when the given input different input data, the frequency divider with a different frequency di
Freq_gen
- XILINX 分频器 100MHz，1KHz， 1Hz(XILINX frequency divider 100MHz, 1KHz, 1Hz)
7_1
- 电路端口为：异步清零输入端口rst，输入时钟clk_in，输出时钟clk_out。并分别采用两种以上的方法实现。(Frequency divider circuit port is: Asynchronous Clear input port rst, input clock clk_in, output clock clk_out. And use two or more methods to achieve.)
verilog_PLL
- 全数字锁相环的verilog源代码，包括鉴相器，K变摸可逆计数器，加减脉冲器和N分频器。已经仿真实现。(All digital phase-locked loop Verilog source code, including phase discriminator, K variable touch reversible counter, add and subtract pulse and N frequency divider. Have been implemented by simula
FPGA_test_20170620_1
- 对50M的系统时钟进行分频处理，然后控制led的闪灭(Frequency divider controls led.)
AD9512_SPI_Config
- 用户可以通过各分频器改变一路时钟输出相对于其它时钟输出的相位，这种相位选择功能可用于时序粗调。(The user can change the clock all the way through the frequency divider output relative to other clock output phase, the phase selection function can be used for timing coarse adjustment.)
fenpin51
- 任意整数分频器，输出方波可调占空比（已仿真下板子验证）第一个系数为分频系数，第二个为高电平所占整个方波的比例(Arbitrary integer frequency divider, output square wave adjustable duty cycle (has been simulated under board verification), the first factor for the frequency division coefficient, the second fo
uart_rxd
- 用Verilog实现UART，有分频模块，可调整波特率(UART with Verilog, there are frequency divider module, can adjust the baud rate)