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floating_point_multiplier_verilog
- This code has written in verilog and it can multiply two floating point number with IEEE 754 standards and the out put of this code is in IEEE 754 standard.We have to put input in binary and the out put is also in binary.
FloatingPoint-Adder
- Implementation of 32-bits Floating Point Adder, based on IEEE 754 Standard
FloatingPointMultiplier
- Implementation of 32-bits Floating Point Multiplier, based on IEEE 754 Standard
ibm2ieee
- 将ibm格式转为ieee-754。编码转换。自己写的。验证过。常用于地震数据。-ibm to ieee
FPU
- 32位单精度浮点运算单元,遵从IEEE 754标准，持浮点加、减、乘、除等运算。-32-bit single-precision floating-point unit；comply with the IEEE 754 standard；support floating-point add, subtract, multiply operations.
IEEE-754
- 4bit to 单精度浮点数转换……上位机处理单片机浮点数时一定会用到……基于labview2012-4bit to IEEE745
s_logb
- IEEE 754 logb. Included to pass IEEE test suite.
ieee754_32
- Converts a floating point value to IEEE 754 32 bit binary representation. Sign Bit: 1 Exp: 2 to 9 Frac: 10:32 Single-precision floating-point format is a computer number format that occupies 4 bytes (32 bits) in computer memory and r
Code
- IEEE-754 Floating-Point Conversion From 32-bit Hexadecimal Representation To Decimal Floating-Point in 8051.. Usable PID and PLC and mostly 485 anable devices for Read Floating Data-IEEE-754 Floating-Point Conversion From 32-bit Hexadecima
math_efp
- This file is the exception handler to make E500 SPE instructions fully comply with IEEE-754 floating point standard.
s_frexp
- IEEE 754 logb. Included to pass IEEE test suite. Not recommend. Use ilogb instead.
s_significand
- for exercising the fraction-part(F) IEEE 754-1985 test vector.NDK r8d: Add android_setCpu().
ieee_test
- IEEE functions for satisfying IEEE 754 test.
fpu_double
- The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard f
half_float-master
- half_float: C implementation of a 16 bit floating-point type mimicking most of the IEEE 754 behaviour. Compatible with the half data type used as texture format by OpenGl/Direct3D.
SVM
- State vector machine with single class output. The code works on 32 bit numbers in IEEE 754 floating point format for single precision numbers.
VHDL-Samples
- VHDL Samples，8-bit calculator controller；vending machine controller with typical vending machine logic ；mplements (most of) the logic required to implement a IEEE 754 multiplier unit.
floatConvert
- 根据IEEE754规定写了个float型数据与二进制数转换的方法-According to the provisions of the IEEE 754 wrote a float data and binary conversion method
adder
- 能够实现单精度浮点加法运算。输入引脚有：第一运算数，第二运算数，复位信号，时钟信号。输出信号有：运算结果，运算完成标志。(To achieve a single precision floating-point addition operations)
Coding Files
- Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double