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ddfsdemo
- 直接数字频率合成器(Direct Digital Frequency Synthesizer:DDFS)的VHDL程序,开发环境是QuartusII,系统时钟为50MHz,由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位,频率字为20,相位字为10,RAM用于存储查找表,其地址位宽为10,数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development enviro
vhdl2
- 在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意-QuartusII warning solving
FPGA
- 有关FPGA的一些资料以及个别源程序,编辑环境为quartus 主要有:电子设计竞赛优秀论文 ----相位测量仪 采用高速AD的存储示波器设计 基于FPGA的多种分频设计与实现 兼容ALTERA公司的USB Blaster下载线的原理图和PCB文件 FPGA与单片机的接口程序 FPGA的大量课件和实验源代码资料 FPGA七段译码器的设计 QuartusII学习资料-FPGA QuartusII
opencore_crt
- 可以在Altera QuartusII下编译的Open Cores PCI桥源代码,是经过多天辛勤整理修改才完成的-Open Cores PCI bridge source code that can be compiled at Altera QuartusII. Modified under many days of hard work
e7v4
- 数字钟:显示,设置时间,设置闹铃(报时),秒表。 平台:quartusII 5.1。 说明:此版本中已将系统时钟调快,自己稍微改动一下即可,小小的考验,做出来会更有成就感!-digital clock:display time, set time, set alarm(use speaker to alarm), stopwatch. platform: quartusII 5.1 comment: there s a place to change if you want th
wishbone_i2c_master
- 本帖最后由 NovaCao 于 1-18-2009 18:02 编辑 使用Quartus II进行仿真 QQ:44425312 QQ群:50585234(群名称:FPGA4u) gtalk:fpgaforu@gmail.com 网站:www.fpga4u.com 淘宝网店:http://shop34914329.taobao.com/ 我们以一个计
iic.cx
- 本帖最后由 NovaCao 于 1-18-2009 18:02 编辑 使用Quartus II进行仿真 QQ:44425312 QQ群:50585234(群名称:FPGA4u) gtalk:fpgaforu@gmail.com 网站:www.fpga4u.com 淘宝网店:http://shop34914329.taobao.com/ 我们以一个计
qinqin
- 串口通信电子琴 QUARTUSII 和VB程序-Serial communication keyboard QUARTUSII and VB programs
Crack_patch_license
- Quartus II 6.0 破解补丁和license设置-Quartus II 6.0 crack patch and license settings
KeyBoard_ysd
- quartusII的环境下的基于Ep3C10144的KeyBoard程序-quartesII of the environment based on the KeyBoard program Ep3C10144
QuartusIIuserguide
- 收集的QuartusII的使用手册,包含了几个pdf文件,比较不错的参考手册-Collected QuartusII s manual contains a number of pdf files, compare a good reference manual
example
- 自己编写的经过QuartusII验证的Verilog HDL程序,可以实现常见功能-After QuartusII their written procedures for verification of the Verilog HDL, can achieve common features
Nios_II_I2C
- 本源码为Nios II的开发示例,主要演示Nios II的I2C总线设计。开发环境QuartusII。 本示例十分经典,对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II I2C-bus design. Development environment QuartusII. This example is very cl
Nios_II_SPI
- 本源码为Nios II的开发示例,主要演示Nios II的SPI总线设计。开发环境QuartusII。 本示例十分经典,对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II design of the SPI bus. Development environment QuartusII. This example is
Nios_II_uCOS
- 本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。 本示例十分经典,对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is
nios_lcd_3c120
- Cyclone III FPGA Nios II LCD开发程序,包括QuartusII工程及Verilog源码。-Cyclone III FPGA Nios II LCD development process, including the QuartusII engineering and source code.
qiduanma
- 用verilog描述的七段码程序,包含测试文件,经过了quartusii仿真测试并成功下载到DE3板子-Described in the seven-segment code with verilog program, including test file, after quartusii simulation testing and successfully downloaded to the board DE3
tarea
- tereas varias desarrolladas y simuladas en herramientas como quartusII y model sim
tut_simulation_verilog
- This tutorial introduces the basic features of the QuartusII Simulator.
speed_test
- QuartusII运行环境下的计数器的VHDL源代码,其中有部分文档说明。-QuartusII operating environment under the counter VHDL source code, some of them documented.