搜索资源列表
Design-AND-gate
- 通过应用QUARTUSII开发软件对与门的设计（二输入）和D触发器的设计。 -QUARTUSII development through the application of software and door design (two inputs) and the D flip-flop design.
Multiplexer-Description
- 通过应用QUARTUSII开发软件对二选一多路选择器进行设计并运行结果-Software development through the application of QUARTUSII choose one of two multiplexer design and operation results
Multiplexer-Description2
- 通过应用QUARTUSII开发软件对 四选一多路选择器进行设计，并给出运行结果-Software development through the application of QUARTUSII choose one of four multiplexer design, and operating results are given
3-8-encoder-design
- 通过应用QUARTUSII开发软件对3—8译码器进行设计，给出运行程序和结果-Development through the application of QUARTUSII 3-8 decoder software for design, operational procedures and results are given
Describe-counter
- 通过应用QUARTUSII开发软件对用if语句描述二进制（M＝10）计数器进行设计，并给出运行结果-Software development through the application of QUARTUSII if statement with the descr iption of the binary (M = 10) counter design and operation results are given
IR
- 利用verilog编写的红外线接收解码电路，开发环境为altera板，quartusII仿真并在开发板上验证通过-Prepared using verilog infrared receiver decoder circuit, the development environment for the altera board, quartusII simulation and validated by the development board
vga
- 基于QuartusII 6.0 环境的vga驱动程序，所用芯片为EP1C6Q240C8,开发板时钟50M，显示模式800*600，72Hz，内容是在频幕显示几条直线。-Environment based on QuartusII 6.0 vga drivers, the chips for the EP1C6Q240C8, development board clock 50M, the display mode 800* 600,72 Hz, the frequency content of
txc_ad9957ctrl
- ad9957芯片配置程序，包括将并行18位数据专程spi口传输。基于quartusII创建-ad9957 chip configuration procedures, including a special trip to the parallel 18-bit data transfer spi port. Created based on quartusII
quartusII-licence
- Altera.Quartus.II6.0破解文件，对FPGA学习有用-Altera.Quartus.II6.0 crack file, learn useful for FPGA
FPGAstudything
- 丰富的FPGA与VHDL学习资料，其中包含：fpga很有价值的27实例、fpga很有价值的27实例、quartusII详细使用指南、电路设计[FPGA]设计经验-FPGA and VHDL-rich learning materials, which includes: fpga valuable 27 instances, fpga valuable 27 instances, quartusII detailed user guide, circuit design [FPGA] desig
VHDL-SUBWAY
- 基于QuartusII环境下的地铁自动售票系统-Subway auto ticketing system based on QuartusII
nios_web
- 基于Nios的CPU软核设计实现，quartus-Nios soft core CPU based on the design and implementation, quartusII
zq_100us
- 利用VHDL实现偶数分频，设计了一种能够实现等占空比的任意偶数分频、等占空比任意奇数分频、不等占空比的任意半整数分频的较为通用的分频器,并通过QuartusII进行了功能仿真。 -Use VHDL to achieve an even frequency, designed to achieve such a duty cycle of any even frequency, such as the duty cycle divide any odd number, ranging from
Memory
- Single Clock Synchronous RAM Design Example with Quartus-Single Clock Synchronous RAM Design Example with QuartusII
quartus2
- quartusII实用指南，对了解和学习quartusII很有帮助的。 -quartusII practical guide to understanding and learning quartusII helpful.
QuartusII-for-chinese
- verilog设计练习进阶,很好的练习资料-Advanced verilog design practice, good practice information ,,,,,,,
counter_20
- 20计数器，quartusII编写，VHDL语言-20 counters, quartusII writing, VHDL language
FIR_IP_lowpass
- 8阶FIR_IP的VHDL代码以及QuartusII的顶层文件-FIR_IP the VHDL code of order 8 and the top-level file QuartusII
vhdl-coding-procedures
- vhdl coding procedures 是在quartusII 下用VHDL编写的 包括了双极性码编hdb3码 和用3位二进制码编hdb3码 -vhdl coding procedures in quartusII prepared under the covers with the VHDL code compilation hdb3 bipolar code and binary code compiled using three hdb3 code
detect
- 基于QuartusII的序列检测器，可下载到实验箱-Based on the sequence QuartusII detector, can be downloaded to test me