搜索资源列表
scan_led
- 基于QuartusII的三位10进制数码管显示电路-Base 10 based on the three QuartusII digital display circuit
ug_fft_2011
- ALtera 公司 QuartusII 软件中FFT Megacore 用户手册，2011年最新官方版！-ALtera company QuartusII software FFT Megacore user manual, 2011, the latest official version!
ook
- 产生OOK的随机码，可以用于QuartusII中ROM或者RAM中。-OOK generated random code, can be used to QuartusII of the ROM or RAM.
mimasuo_design
- 这是一个基于quartusII平台，利用VHDL软件编写的关于密码锁的程序，里面把密码锁详细分解为输入模块、密码模块、控制模块以及一个密码锁的总体设计，详细介绍了密码锁的控制过程。-This is based on quartusII platform, software development using VHDL program on lock, which locks in detail the decomposition of the input module, the cryptogr
ADSample_FPGA
- 开发环境为QuartusII。这是AD采样的verilog代码部分，在FPGA上硬件实现AD采样的一部分功能-Development environment for the QuartusII. This is the verilog code for part of the AD sample, the FPGA hardware on the part of the function AD sampling
da1_test
- ad转换，采用Altera Cyclone FPGA (EP1C6-PQ240)芯片， 在QuartusII 9.0 下编译，有较好的参考价值，已通过测试。-ad conversion, using the Altera Cyclone FPGA (EP1C6-PQ240) chip, in QuartusII 9.0 compiler, a better reference value, has been tested.
ad1_da1_test
- 将第一路AD转换结果输出给第一路DA ，在QuartusII 9.0下编译，有较好的参考价值，已通过测试。-The first road to the first AD conversion result is output Road DA, compiled in QuartusII 9.0, there is a good reference value, has been tested.
Verilog
- QuartusII编译与仿真之warning解析,设计示例,verilog中reg和wire类型的区别.-QuartusII compilation and simulation of warning analysis, design example, verilog in the difference between reg and wire type.
DDS_FSK
- 该软件能实现FSK的调制功能，在quartusII上进行了仿真，效果非常好-The software enables the FSK modulation capabilities, in quartusII on the simulation results is very good
InfraredPort
- 实现红外接收的源码，能够从端口获得所接收到的红外数据。采用QuartusII实现，可以直接连接NiosII。-The source for infrared receiver, from the port to the received infrared data. Using QuartusII achieve, can be connected directly NiosII.
exp2prj1
- 基于FPGA的DDS，编写语言为verilogHDL，编辑环境为quartusII 9.0，dds频率可程控调节-a Direct Digital Synthesis based on FPGA
fsk
- 这个是基于quartusii 和dspbuilder与matlab的fsk的实现，希望对大家有用。加油-This is based on the quartusii and dspbuilder with the fsk matlab implementation, I hope to be useful. Oil
DDS
- 这个是在quartusii和matlab simulink下搭的dds的模型，已经经过仿真是可以的。并且已经转为vhdl代码。-This is quartusii and matlab simulink model to catch the dds, has been the simulation is possible. And has to vhdl code.
cos_val
- 用matalb实现QuartusII中的初始化文件（.mif或是.hex)文件，涉及到matlab中文件的读写步骤。-Realize the initial files(.mif or .hex) using matlab,and it involves writing and reading in matlab.
1day11-keyboard
- 清华大学电子课程设计：Verilog语言编写，可在QuartusII完全正确运行，FPGA下载，键盘按键输出相对应数字，有防抖功能-Verilog language, can be run in QuartusII entirely correct, FPGA download, keyboard keys corresponding to the output figures, anti-shake function
task2
- Verilog语言，可在QuartusII正确运行，实现远程控制系统，利用异步串行通信，PC发送数据FPGA接收，实现本地回环模式。-清华大学电子课程设计：Verilog language, you can QuartusII correctly, remote control systems, using asynchronous serial communication, PC to send data received FPGA to achieve the local loopback
calculator_final
- 清华大学电子课程设计：Verilog，QuartusII可正确运行，可下载到FPGA上，音乐计算器，完成两个三位数的运算，有注释，很强大-Verilog, QuartusII run correctly, can be downloaded to the FPGA, music, calculator, completed two three-digit operations, there are notes, very powerful! !
cal
- 运用quartusII vhdl语言做成的计算器-Made use of quartusII vhdl calculator language
clock
- 利用quartusII vhdl做成时钟-Made use of quartusII vhdl clock
Manchester_QuartusII
- 完整的曼彻斯特编解码(采用锁相环技术）_QuartusII工程-A complete QuartusII project for Manchester coding and decoding with phase-locked loop technology