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verilog--divide-programs
- verilog任意分频程序，包括奇数倍分频和偶数倍分频，占空比为50 ，QuartusII上验证程序有效-verilog every divide programs, including an odd multiple divider and even multiple frequency, duty cycle 50 , the QuartusII on the verification process
fenpinqisheji
- 设计的是一个带复位的分频器，输入时钟为60MHz，输出时钟为7.5MHz。经过quartusII仿真过了的-The design is a reset of the divider, the input clock is 60MHz, the output clock is 7.5MHz. After quartusII simulation over the
key_test
- verilog HDL编写的在quartusii环境下的24秒倒计时代码-verilog HDL the quartusii environment in the 24 seconds countdown code
QuartusII-about-warning
- 主要是介绍quartus编译过程中出现的问题和解决方法，希望对大家有帮助-Introduce the quartus compile process problems and solutions, I hope to you
mux21a
- 应用QuartusII 完成基本组合电路设计-The application QuartusII completion of basic combinational circuit design
mul1617
- 采用verilog RTL级语言，实现了有符号的16位乘17位的乘法器。特点是：采用流水的结构，可以在一个周期内处理完数据。通过QuartusII和Modulesim的功能仿真和时序仿真，并得到正确结果。-Realize the signs of 16 of the 17 patients take on time-multiplier. Features are: the structure of water, can be in a cycle processes the data. Thr
7_SEGMENTLED
- 在DE2开发板上，通过在Altera QuartusII软件中编写.v代码，驱动DE2开发板上的7段数码管。-DE2,verilog,altera quartusII,7segmentled
quartus2
- 这是一本quartusII的中文经典教程，内容丰富，讲解详细，非常值得一看-This is a quartusII Chinese classic tutorials, rich in content, the explanation is detailed, extremely is worth a look
IR
- FPGA实现的红外IR解码程序，已成功通过Quartus编译，可实现红外正确接收和数据解码提取。-This is a verilog IR decoding program. It has been already compiler through the QuartusII.
FPGA-and-SOPC
- quartusII中有个sopcbulider工具，此教程很好的介绍了在DE2-70板上如何使用sopcbulider和NIOSII.-It have sopcbulider tool quartusII this tutorial a good introduction to how to use sopcbulider and NIOSII- based on the DE2-70 board.
QuartusPII-USETestbench-MELTHD
- QuartusII使用modelsim的方法-QuartusII use modelsim
pinlvji
- 简单介绍EDA技术的发展现状,着重介绍基于EDA技术的可编程逻辑器即八位数字频率计的设计方案选择、原理图设计输入、原理图编译和仿真等操作,比较完整的说明了八位数字频率计的功能与作用和使用QuartusII软件进行可编程逻辑器件设计的操作流程。 -A brief introduction of EDA technology development present situation, introduced the EDA technology based on programmable log
fft256
- 利用quartusII提供的FFT IPcore设计的256位的FFT，并附有testbench文件-Provided by quartusII the FFT IPcore design 256 FFT with testbench file
traffic-light
- 用vhdl编写的交通灯程序，开发平台为quartusII。调试好的工程文件，可直接下载到实验箱-Written with vhdl traffic light program, the development platform for quartusII. Good debugging project files can be downloaded directly to the experimental box
Sdram_Control_4Port
- 使用verilog HDL写的sdram(SDR)的控制器源代码，具有很好的可移植性，试验的例子已经通过QuartusII 9.0编译通过，可以运行在cycloneII上-Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII
FM_DemodNew
- FM接收机 基于FPGA的调频收音机的设计 用VEIRLOG语言编程，利用QUARTUSii与MODELSIM联合仿真-FM receiver on FPGA FM receiver design With VEIRLOG language program, use QUARTUSii and MODELSIM joint simulation
miniprinter
- 微型打印机模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。 在quartusII里面添加uart核，nios II的Console构成人机交互界面，串口与微型打印机通信，打印出数据。 -Micro printer module experiment rar core on the FPGA-2C35 Borch experimental box platform. QuartusII inside to add the uart nuclear, nios II Con
dianzheng
- 能在FPGA的板子上实现点阵的功能，利用QuartusII软件-Lattice function, use QuartusII software on the FPGA board
Pseudo-random-sequence-generator
- 通过MATLAB的SIMULINK模型设计，实现伪随机数的序列发生器，并通过DSP BUILDER中的SIGNAL COMPILER转换成QuartusII工程，并实现硬件的下载。-Through the MATLAB SIMULINK model design, realization of pseudo random sequence generator, and through the DSP BUILDER of SIGNAL COMPILER converted into Quartu
Controllable-sine-signal-generator
- 通过MATLAB的SIMULINK模型设计，实现可控正弦信号发生器，并通过DSP BUILDER中的SIGNAL COMPILER转换成QuartusII工程，并实现硬件的下载。-Through the MATLAB SIMULINK model design, realization controllable sine SIGNAL generator, and through the DSP BUILDER of SIGNAL COMPILER converted into QuartusI