搜索资源列表
keyqudou
- fpga verilog hdl 设计键盘去抖动程序，设计环境quartusii 9.0。仿真绝对通过。-fpga verilog hdl design keyboard to jitter program design environment quartusii 9.0. Simulation absolutely pass.
mux4booth
- fpga 使用verilog hdl 语言，quartusii 9.0编程环境，使用2booth算法设计的4bit乘法器。可以扩展为16bit乘法器。-fpga verilog hdl ，quartusii 9.0 ，2booth 4bit
top_module
- fpga 使用verilog hdl 语言，quartusii 9.0编程环境，设计的4个led灯分别实现不同功能，然后由一个顶层文件调用，完成总的设计。-fpga using verilog hdl language, quartusii 9.0 programming environment designed four different functions, respectively, led lights, followed by a top-level document called,
Quartus-VHDL-lms
- 使用VHDL语言在quartusII中实现自适应滤波算法-The filtering algorithm
bit7_Binary_to_BCD_LED
- 二进制转十进制BCD码 Verilog语言 quartus-Binary to decimal BCD code Verilog language quartusII
zdsylj
- 自动售饮料机，在quartusII平台上实现verilog源代码。很好用。-Beverage vending machine, quartusII platform to achieve verilog source code. Good use.
sdram
- sdram的quartusii实验源代码，和大家分享。很好用，我在自己的开发板上实现了他的功能，大家试一下。-sdram of quartusii experiment source code, and share. Very good, in my own development board realize his function, we try.
dgnszsz
- 多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。-Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.
hlh
- 绿灯、黄灯和红灯，交通灯实验veril源代码，与大家分享，在quartusII平台上实现。-Green, yellow and red lights, traffic lights experiment veril source code, to share with you, in quartusII platform.
zwcfq
- 带置位和复位端的1 位数据锁存器，源代码verilo实现，在quartusII平台上，大家试试看。-With set and reset terminal a data latch, the source code verilo achieve, in the quartusII platform, we try.
1602test
- Verilog AD转换1602显示，用QuartusII编写的。完整的工程，好使！-Verilog AD converter 1602, with QuartusII prepared. Complete works, so that!
pingpongf16
- 使用quartusii软件,用verilog语言编写，通过DE2-70板在屏幕上实现乒乓球动态效果。-Use quartusii software, using verilog language, through the DE2-70 board on the screen to achieve tennis dynamic effects.
freq_viewer
- quartusii下基于原理图方式构建的频率计，在altera cyloneIII 芯片上已经验证成功，精度为1Hz-quartusii under way to build a schematic-based frequency meter, in altera cyloneIII chip has proved to be successful, the accuracy of 1Hz
ramIPcore
- 基于quartusII的ram调用，利用FPGA自身的blockram创立ram的ip core-Based on the ram quartusII calls itself blockram created using FPGA ram' s ip core
fpga_fenpin
- 这个是根据fpga芯片写的分频模块，modelsim综合，QuartusII测试-This is the fpga frequency module, modelsim comprehensive, QuartusII test
Verilog-language--de-CPU
- 基于verilog语言的FPGA开发，平台在QuartusII上，对SDRAM的读写-Verilog language based FPGA development platform on QuartusII, the SDRAM read and write
Md5Sopc
- 在Altera平台上实现Md5算法的IP核 modelsim进行MD5硬件代码的仿真和测试 quartusII 和nios软件实现ip核和驱动程序 已经测试程序的仿真和测试 代码调试通过 -Md5 algorithm simulation and test implementation in the Altera IP core platform modelsim the MD5 code simulation and test hardware and quartusII ip nios so
pcf8563
- pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示-pcf8563, written in quartusII VERILOG digital clock program, eight digital display
Quartus_II_11.0
- QuartusII.11.0学习与应用，QuartusII.11.0的入门学习与快速应用方法-QuartusII 11.0 learning and application, QuartusII 11.0 introduction to the study and application methods quickly
ASS2_bench
- Verilog HDL for IRDA transmitter by DE2 board using Altera Cyclone II Quartus-Verilog HDL for IRDA transmitter by DE2 board using Altera Cyclone II QuartusII