搜索资源列表
RS_232_2
- RS232串口通讯实验，verilog HDL，在quartusII开发环境下-RS232 serial communication experiment, verilog HDL, in quartusII development environment
signal_tap_ii_test
- Quartusii环境下利用signal tap ii工具进行仿真的实例，很好的参考实例-Under Quartusii environment using signal tap ii tools for simulation examples, a good reference example
20_lcd
- 一种基于verilog和quartusII的液晶显示驱动的封装，LCD（12864）封装。-Verilog and quartusII based LCD display driver package, LCD (12864) package.
iicbus
- 基于Nios II的I2C总线设计,开发环境QuartusII，VHDL，经典示例。-I2C Bus Design Based on Nios II
dds1
- 正弦波的quartusII的函数表 正弦波的quartusII的函数表-Function table
VHDL LCD
- Using VHDL written LCD tool
Quartusdoc
- QuartusII的文件管理，关于QuartusII中各类文档的归类说明。-QuartusII document management, on various QuartusII classified documents indicate.
098111__1367421625730
- DE2_System_v1.4a.zip 71.2M 2007- 02 22:51 For DE2 boards with Serial Number (S/N) starting with Digit 0 and QuartusII version 6.0 DE2_System_v1.4b.zip 79.4M 2007-07-11 22:42 For DE2 boards with Serial Number (S/N) starting with Digit 0
QuartusIIjianming
- QuartusII中文简明使用手册，对于搞硬件开发的初学者很有用。-QuartusII Chinese condensed manual, engage in hardware development is useful for beginners.
moore
- moore状态机，quartusii上仿真通过-moore state machine
CA-code
- 生成CA码verilog代码，quartusII开放环境，含源代码和仿真文件（波形、testbench）-CA generated code verilog code, quartusII open environment, including source code and simulation files (Waveform, testbench)
tanchishe-QuartusII
- VGA显示FPGA实现的VHDL语言的贪吃蛇游戏设计 本设计分为6个模块主要是扫描模块 VGA现实和控制模块 游戏设计的模块 电源模块等 用QUARTUS2仿真运行-VGA display FPGA VHDL language to realize the Snake game design The design is divided into six modules mainly scanning module VGA module power module and contro
Multi-function-digital-clock
- QuartusII开发的EDA 采用两个双十进制计数器74390 以及其他部件 组成了具有暂停 清零 调时针 调分针 12 24进制转换 整点报时等功能的多功能数字钟-QuartusII EDA developed using two pairs of decimal counter 74390 as well as other components of tune with the suspension cleared tone hour minute 1224 hex conversion
code
- 设计RS、JK、D、T 四种触发器，掌握异步复位置位的方法以及四种触发功能的实现方 法，掌握QuartusII 软件的使用方法以及GW48 型SOPC 开发平台中的输入输出模式配置方 法。 -Design RS, JK, D, T four kinds of triggers, grasp complex bit asynchronous methods and how to configure four trigger implementation function Quartu
四位计算器
- 实现四位数的加减运算，基于verilog语言编写，quartusII编译通过
LED
- QuartusII 9下的LED灯示例，很简单的例子，可以直接运行-The sample of LED of quartus II 9.0 with the language of Verilog
Simple_Logic_Continue
- quartusII 9编写的74161模块，简单的例子，可以直接运行-The module 74161 with the language of verilog
eda-example
- 初学者福音，有70个基于FPGA VHDL开发历程，可以通过这些文件下载到QuartusII中，做实验-Beginners, there are 70 VHDL based on FPGA development course, can download the files to QuartusII, doing experiments
CRACK
- quartusII的软件的使用，对学习FPGA是有用的，希望对大家有用，希望大家喜欢。-Use quartusII software, it is useful to learn FPGA, we want to be useful, I hope you like it.
count_minut2
- verilog语言编写的电话计费器程序,编程环境为quartusii，实现了接电话、打电话、计时、分段计费、话费充值、欠费自动挂断等功能。-verilog language telephone billing program, the programming environment for quartusii, realized the phone, call, timing, staging billing, prepaid recharge, automatically hang up ar