搜索资源列表
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
VHD
- RS编码中用到的交织和去交织程序，VHDL描述，交织深度8-nterlace with VHDL，depth is 8
rs232_transmit_control
- RS-232 transmir control programmed in VHDL
byzxin_RS232
- RS 232 interface vhdl language programme for video processing pcb board.
Trigger
- 各类触发器VHDL源码程序，在quartus-ii7.2版本上测试通过，文件中包括D触发器，JK触发器，RS触发器，T触发器。-Various triggers VHDL source code program in quartus-ii7.2 version of the test is passed, the document includes a D flip-flop, JK flip-flop, RS flip-flop, T flip-flop.
asynchronous-sequential-circuits
- 利用基本RS触发器设计电平异步时序电路的方法 此文档帮助读者设计数字逻辑电路，并非VHDL语言实现-The use of the basic RS flip-flop design level asynchronous sequential circuits This document is to help readers design digital logic circuits, not the VHDL language
PipelineCPU
- 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt
mulitcpu
- 用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs,
091220111singalcpu
- 用verilog HDL语言或者VHDL语言来编写，实现单周期CPU的设计。能够完成以下十六条指定： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti
rs232
- this is vhdl code. purpose of rs-232 connected with altera cyclone2.
RS_coding_123
- RS编码的实现，包括C语言，C++，java，VHDL，DSP，matlab的RS编码实现，代码全部调是通过。-RS encoded, including the C language, C++, java, VHDL, DSPs, Matlab the RS coding, the code all the tune through.
rs232_receiver
- receiver RS-232 programmed in VHDL
rs422
- RS-422的VHDL实现，代码测试能用-RS-422 VHDL implementation code test can be used
188135a9844b
- rs(204,188)译码器VHDL语言源代码-failed to translate
82be270ea751
- RS（255，239）编码器的VHDL语言源代码，希望能对大家有一定帮助-the code of the encoder of rs（255,239），hope can help you
rschufaqi
- 此程序是根据rs触发器的功能用VHDL语言描述的RS触发器，供同学们学习交流-This program is based on the RS flip-flop rs flip-flop functions described in VHDL language for students learning exchanges
URAT
- 在ISE环境下，用VHDL语言实现RS232串口设计，实现串口通信。通过串口调试工具向 0000000UART发送16进制数，FPGA将UART接收到的串行数据转换为并行数据，并在8个 LED灯上输出显示；同时，并行数据又被重新转换为串行数据，重新送给RS-232接口，并在 串口调试工具上再次显示，SW0为复位键。 比如：串口调试工具发送两位16进制数，然后能在LED上显示，并且重新在串口调试工 具上显示。串口调试工具设置：波特率设为9600，默认奇校验。-In the IS