搜索资源列表
RS232
- FPGA实现RS-232串口收发的Verilog程序，已经调通。
RS_decoder
- 高速RS编码算法及FPGA实现,一篇文章,写的很好,介绍了接收机中常用的RS编码的原理,指标与实现,觉得有用就看看吧.
1
- RS译码的Euclid算法及其FPGA实现
2
- 基于FPGA自适应高速RS编译码器的IP核设计
rs_encoder
- 一个很不错RS编码，用于DVB的信道编码，用VHDL语言编写，在FPGA上通过验证。
RS_Euclid_FPGA
- RS译码的Euclid算法及其FPGA实现，并通过仿真器的出结果，对于设计ＲＳ译码很有帮助
GF_2_m_FPGA
- GF_2_m_域乘法器的快速设计及FPGA实现，对于rs编翼码的理解和设计有帮助
RS485EN
- RS485的双向通信处，正在为此头疼的同学们可要注意了，这个可以解决你们双向通信过程中的很多问题哦-Two-way RS485 communications, the headache is to this end they' ll pay attention to the students, this two-way communication you can solve many problems in the course of oh
RSencode
- 基于FPGA的RS编译码器实现 我是新手 刚学的写的很简单的代码 -FPGA implementation RS codecs
RSandfpgadesign
- 详细介绍了RS编解码背景以及原理，同时给出了FPGA实现方案-Described in detail the background of RS codecs as well as the principles of the FPGA at the same time give the realization of the program
c_FPGA
- RS232设计，硬件测试通过，VERILOG实现的，比较好的哦-RS232 design, hardware test, VERILOG realized, oh good
RS_FPGA_papers
- 两篇RS编码fpga仿真的硕士论文，看完会对RS编码及其硬件实现步骤有清晰的理解。-2 RS codes fpga simulation master' s thesis, after reading the RS coding and hardware implementation will have a clear understanding of the steps.
verilogRS
- 该文件为基于fpga的RS（204.188）译码器的verilong源代码，使用的Quartus II的开发环境，已经通过编译，需要者可以自己下载在编译简历工程使用-The document is based on fpga' s RS (204.188) decoder verilong source code, use the Quartus II development environment, has been compiled by the need to download th
jishuji
- 将基本RS触发器，同步RS触发器，集成J-K触发器，D触发器同时集成一个FPGA芯片中模拟其功能，并研究其相互转化的方法。-The basic RS flip-flop, synchronous RS flip-flop, integrated JK flip-flop, D flip-flop while a FPGA chip analog integrated function, and to study their mutual transformation method.
new_RS_Verilog
- 这是基于FPGA的RS编解码的实际例子。我已经调试完成！- This is arranges the decoding based on FPGA RS the actual example. I already debugged complete!
RS-232CUART
- 主要是利用FPGA进行串口的通信 其中利用到FPGA的开发软件QUARTUS -verilog NIOS UART
RS-deRS
- 总体设计RS编码解码方案，分析各种RS编码方式，并在FPGA上实现，证明设计可行性。-The overall design of RS encoding and decoding schemes, analysis of various RS encoding and implemented on the FPGA, to prove the feasibility of the design.
rs_code
- FPGA实现了RS（255，239）的编译码模块(FPGA implements the RS (255239) encoding and decoding module)
RS
- 本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（ ）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS
Zircon_Digital
- 多选一多路器，三人表决器，触发器，RS寄存器(Choose a road, three people vote, trigger, RS register)