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FIFOed_avalon_uart9.10
- nios II avalon fifoed uart used in SOPC
uart
- 单片机串口通讯和温度采集-MCU-UART
uart
- 串口FPGA实现，采用了状态机的方案 串口FPGA实现，采用了状态机的方案-FPGA UART
uart
- 一个串口程序，用定时器作为波特率发生器，只要知道波特率便可以直接初使化uart，具有很强的适应能力的程序-A serial program, with the timer as a baud rate generator, as long as they can directly know the baud rate initialization uart, has a strong ability to adapt procedures
msp430timerauart
- using timer a for uart for msp430
resuart
- interrupt based software uart for pic18f
uart_driver
- uart coding for pic 16F877A micro controller its is used to communicate with pic and personal computer its fully working program
uart
- STC12C5A16AD UART串口程序 STC12C5A16AD UART串口程序
lm3s811_evalboard_gcc_20061111d
- lm3s811 is a evaluation board build to luminary microcontrollers. This code ready to uart, timer, gpio, and more.
lpc_2129_uart0_irq_20050514
- This source code example demonstrates the use of UART in a LPC2129 from NXP.
UART
- the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
fifoed_avalon_uart9.1_applicaton
- 用于Altera Avalon总线的、具有FIFO缓冲的Uart数据串口IP核以及应用于Nios2的、真正可运行的、容易移植的C代码。-Fifoed avalon uart IP core and C code for the IP core.
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
uart
- the uart model is used to design the synthies and beherival model in verilog fpga
STR7ProgusingUARTIAP
- STR7_Prog using UART-IAP
PIC_UART
- pic18f4520使用uart做rs232或rs485與電腦pc做連線資料傳輸 內容簡單 從IC腳位設定到啟動UART功能與接收中斷和傳送資料-pic18f4520 use uart do rs232 or rs485 to do to connect with computer pc data transfer is simple and from the IC pin set to start the UART interrupt function and to receive and
uart
- 此文档为C51单片机串口通讯学习程序（中断+FIFO)-This document is for the C51 microcontroller serial communication learning process (interrupted+ FIFO)
uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
dlt645-1997
- c51 buffer uart使用 协议解码 dlt645-1997-c51 buffer uart
ser.tar
- serial examples with user defined uart baud rate for linux-serial examples with user defined uart baud rate for linux