搜索资源列表
test_uart
- uart VHDL code : include tx,rx,parity bit control
uart_tx_rx
- 该工程用verilog编写，已通过串口调试助手调试通过，接收模块采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。-Verilog prepared by the project, has passed through the serial debug debugging assistant, receiving 8 times the baud rate module sampling data, a better filtering in the PC to complet
UART
- Verilog实现的UART程序，用ISE打开工程文件即可-Verilog implementation UART program, open the project file with the ISE can be
i2c_AT24C04_Verilog
- 用Verilog HDL语言编写的AT24C04程序，并用数码管显示，已经过测试，很好用-With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use--
UART
- Verilog HDL写的实现ＵＡＲＴ收发程序-Realization of Verilog HDL UART receive written procedures