搜索资源列表
simple_fifo
- verilog HDL原码 一种简单的同步FIFO原码,可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated
fifo_datapath
- verilog实现,串转并通过fifo再并转串,可以满足输入速率自由输出的一半时,输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
rs_decoder_31_19_6.tar
- Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
!061210[1].pdf
- 基于FPGA的异步FIFO的软硬件实现,通过VERILOG编程实现后下载到FPGA芯片
syn_fifo
- 同步FIFO的verilog编码 -synchronous FIFO verilog coding synchronous FIFO verilog Synchronous Code FI FOR the verilog coding synchronous FIFO verilog coding
fifo_ver_131
- fifo verilog hdl 源程序-fifo verilog hdl source
FIFO_v
- FIFO的verilog实现,内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
FIFO_Syn
- 同步FIFO功能,verilog语言描述,通过了modelsim 6.0 仿真,Quartue综合
4VerilogFIFO
- 一种新的FIFO实现方法,verilog描述,通过modelsim 6.0 仿真,Quartue综合
eetop.cn_FIFO_Buffer
- 异步FIFO的Verilog程序及其测试程序(FPGA/Verilog FIFO_ASYN)
sdtest
- 这个是一个verilog程序,可以用spi读取sd卡中的内容,存到fifo中(This project can read the data from SD card through SPI interface and store the data in FIFO.)
fifo_controller
- 用verilog语言实现FIFO控制器,控制FIFO的读写过程,有空满标志(Implementing the FIFO controller)
sfifo
- fifo 控制器,也是转载的,主要是为了积分(A fifo controller verilog descr iption.)
uart_fifo_n
- verilog 带fifo的串口收发模块(verilog uart with fifo)
tx_interface_project
- 带FIFO的串口发送模块,简单的FPGA串口发送模块(Serial transmission module with FIFO)
FPGA_USB2.0设计
- 把FX2配置成从FIFO的模式, 配置为单片机工作时钟24M,端点2输出,字节1024,端点6输入,字节1024,信号全设置为低电平有效等。我们的模块驱动时钟我们配置成内部输出时钟,也就是让FX2给我们的设计当做时钟源,输出一个最大的配置时钟48M的时钟。(The FX2 is configured from FIFO mode, configured as MCU working clock 24M, endpoint 2 output, byte 1024, endpoint 6 input
sobel
- 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测,工程文件可在quartus13.1以上版本打开;工程使用到ram、fifo、pll三种ip核,design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块,sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果;测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化,再将生成文件中数据用串口发给FPGA,边缘检测结果会通过VGA输出。(Written by Ve
FIFO_UVM
- fifo uvm this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving proper output(this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving prop
通信协议FPGA
- 本设计是基于FPGA的高速并行接口通信接口和协议设计,该设计使用的是8 位并行接口,通过配置FPGA的FIFO寄存器保证了在高速并行下的数据稳定性,在 最终的测试中,该协议能够稳定传输的速度为80Mbps。(This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8 Bit parallel interface
Verilog实例代码
- 一些verilog模块的代码与tb,常见的同步异步FIFO,RAM和适合新手学习