搜索资源列表
DS_Receiver_Design
- 扩频接收机设计实例(VHDL\\MATLAB)
kpjsj
- 次源码实现一个扩频接收机系统，用VHDL语言编写，并且有完整得测试程序
m.rar
- 扩频接收机设计的部分，一个用vhdl语言编写的m序列生成器，,A language with vhdl generator sequence m
gps_tracking
- 澳大利亚新南威尔士大学研究的GPS接收机的FPGA跟踪模块的.v程序，包括载波跟踪环路、码跟踪环路、通道累加等模块。-The University of New South Wales, Australia, the study of the FPGA tracking GPS receiver module. V procedures, including the carrier tracking loop, code tracking loop, the channel accumulati
GPS.RAR
- 本工程包含了一个GPS接收机的基带处理模块，包括信号捕获和跟踪、电文解调等-The project includes a GPS receiver baseband processing modules, including signal acquisition and tracking, message demodulation
GPS
- 国外一个大学的详细软件接收机M文件,在MATLAB环境下可以运行-asoft-definedgpsreceiver
ca
- 基于vhdl/verilog的gps接收机伪随机码产生程序。已经过仿真综合。-Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
kuoping
- fpga嵌入式设计 扩频接收机设计 有matlab 和vhdl 对比情况-Design of spread-spectrum receiver embedded FPGA design and VHDL contrast matlab
code_gen2
- GPS中C/A码生成电路，用于ＧＰＳ接收机中的跟踪和捕获。-GPS in the C/A code generating circuit for the GPS receiver to track and capture.
simple_fm_receiver.tar
- 一个简单FM接收机的VHDL源码，很有参考意义-A simple FM receiver VHDL source code is very useful
Channel_Equalizer
- 802.11a接收机的信道均衡源码，verilog语言的-802.11a receiver channel equalizer source, verilog language
MatchFilter
- VHDL语言实现8路并行输入，8路并行输出，直接序列扩频接收机的高速匹配滤波。 -VHDL language to achieve 8-channel parallel input, 8-channel parallel output, high-speed direct-sequence spread spectrum matched filter receiver.
fm
- VHDL设计全数字FM接收机 资料大小：650KB 运行环境：Windows -VHDL design of all-digital FM receiver Data Size: 650KB operating environment: Windows
qpsk_relate
- QPSK相关接收机及匹配接收机的verilog实现-QPSK correlation receiver and matching receiver verilog implementation
Receiver
- 该程序是整个OFDM接收机的程序，希望对做这方面的朋友用些帮助，也希望朋友们和我一起探讨OFDM收发信机。-The program is the whole OFDM receiver process, hope to do in this area with some friends to help and also hope that friends and I explore OFDM transceiver.
Spread-Spectrum-Receiver-code
- 基于FPGA的扩频接收机（直扩）vhdl编写的，最好在quartus环境运行。-FPGA-based spread spectrum receiver (DS) vhdl prepared, the best environment to run in quartus.
Rake_Receiver
- 用Verilog HDL语言实现一个Rake接收机的最大比合并准则，其中3路输入数据是并行相关输出-Verilog HDL language with a Rake receiver maximum ratio combining criteria, of which 3 related to the parallel input data is output
Rake-receive
- 本文介绍的一种基于多载波扩频通信的Rake接收机工作原理以及设计思想，并用FPGA技术加以实现-This article describes a multi-carrier spread spectrum based communication works as well as Rake receiver design and implementation with FPGA technology to
nco
- 数字接收机DDS中NCO设计，vhdl代码参考-NCO of DDS in a digital receiver design,vhdl code reference
simple_fm_receiver_latest.tar
- 用FPGA实现简单的FM接收机，d/a模块用扬声器-FPGA implementation using a simple FM receiver, d/a module with speaker