搜索资源列表
SIG_CLK
- 四分频，四个相位的时钟输出，FPGA，vhdl，xilinx-Divided by four, four-phase clock output, FPGA, vhdl, xilinx
xilinx_DDR3-ctl_code
- VHDL语言，xilinx,ddr3 控制代码，已实现-VHDL xilinx DDR3ctl code
VHDL-projects
- I have simple five VHDL projects. I use FPGA Spartan3A family board with XC3S50A FPGA chip. This project was created in Xilinx ISE Design Suite version (13.2).It contains divider,XOR blocks, counters, moore automat and more.
Slides-of-VHDL
- VHDL课件，包括Xilinx软件的入门使用，VHDL基本语法，状态机以及其他。-VHDL courseware, including entry using Xilinx software, VHDL basic grammar, state machines, and others.
Tetris-VHDL
- 利用FPGA和VGA显示器实现的俄罗斯方块游戏。 使用VHDL语言和Xilinx开发。-Using FPGA and VGA monitor to develop a Tetris game. Developed using VHDL language and Xilinx .
BPSK
- BPSK信号的载波调制，包含成型滤波器，上采用器以及载波生成器。(This file provides a transmitter based on BPSK signal, including shaping filter, upsampler and carrier generator.)
szmb
- 用VHDL语言基于ISE，在XILINX FPGA开发板上编写的数字秒表程序(Using VHDL language, based on ISE, in the XILINX FPGA development board prepared by the digital stopwatch program)
ethernet 10-100 monitoring
- this is using mac IP core for ethernet connection in ISE xilinx for ethernet 10/100
he
- 利用VHDL实现判向计数器，并且在数码管上实现显示。可以在XILINX开发板上实现对应功能，仿真也能实现。(The use of VHDL realize the counter counter, and in the digital tube to achieve display. The corresponding function can be implemented on the XILINX development board, and the simulation can also
Half-Adder
- This is an example to implement an Half-adder for xilinx FPGA
AlteraLab1
- To design Fibonacci Sequence using Verilog. SOFTWARES USED: Xilinx Synthesis Tool ISE 9.2i INTRODUCTION. Hardware descr iption language (HDL) is a general-purpose language intended to describe circuits textually,
mealy_state_machine_vhd
- vhdl fpga statmachine
E4_6_FirIpCore
- 用vhdl语言在xilinx上用ip核实现的fir滤波器的设计(Design of FIR filter implemented with IP kernel on Xilinx in VHDL language)
E4_7_IIRCas
- 用vhdl语言在xilinx上实现的iir滤波器的设计(Design of IIR filter implemented on Xilinx in VHDL language)
5_uart_test
- 基于xilinx的Artix7实现UART通信(UART communication based on Xilinx Artix7)
6_eeprom_test
- 基于xilinx的Artix7实现EEPROM的读写(Reading and writing of EEPROM based on Xilinx Artix7)
12_hdma_in_out
- 基于xilinx的Artix7实现HDMI的输入输出(Xilinx based Artix7 implementation of HDMI input and output)
9_ethernet_1g_100M
- 基于Xilinx的Artix7实现千兆以太网的RGMII接口通信(RGMII interface communication for Gigabit Ethernet based on Xilinx Artix7)
can_v3_2
- XILINX 的IP核CAN V3.2的VHDL程序(XILINX's IP core: CAN_V3.2-VHDL)
Xilinx_Vivado_Design_Suite_HLx_Editions_2018.2
- vivado 2018.2 license