搜索资源列表
spi
- spi接口的vhdl实现，所用器件和ip为xilinx的
adc_control
- Xilinx FPGA 开发板的ADC采样源程序 内有PDF文档详细说明 VHDL代码
A8.rar
- 两个进程的并串转换设计，VHDL的Xilinx的开发环境,Two processes and string conversion design, VHDL for Xilinx development environment
VHDL_AES_ZigBee
- 用VHDL实现的ZigBee模块控制算法以及AES加密算法，用于Xilinx的FPGA!-With the realization of VHDL ZigBee module control algorithm and AES encryption algorithms for Xilinx FPGA!
rloc
- RLOC 属性在vhdl code中的直接描述。xilinx的范例文件-Example files for the applicantion of RLOC in Xilinx device.
AssignmentP3
- Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx
xapp687
- xapp687 code from xilinx web down load new-xapp687 vhdl from xilinx web
dpram
- FPGA实现双口RAM的工程文件，直接拿ISE打开即可，或者找里面的.VHD文件也可以-FPGA dual RAM
hardh264
- 一个硬件H264编码的VHDL源码，用于FPGA开发，适合IP摄像头等视频设备输出数据的编码。用Xilinx工具测试过，但代码不只是用于Xilinx。-A hardware h264 video encoder written in VHDL suited to IP cameras and megapixel cameras. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools
HDB3
- HDB3码的编码，图形，功率谱密度。用于通信原理教学等-Code HDB3 coding, graphics, power spectral density. Communication Theory for teaching
xapp514_aes3-audio
- DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
fir
- 用VHDL语言设计有限脉冲响应的FIR滤波器。用户可以在Xilinx ISE环境下运行。-With VHDL language design finite impulse response of FIR filter. Users can run Xilinx ISE environment.
Traffic_Light
- 在XILINX环境下，实现交通信号灯控制，VHDL语言编写。-In the XILINX environment, the achievement of traffic signal control, VHDL language.
DDS
- 《DDS原理简介(中文)》DDS即直接数字频率合成器，原理及系统设计实现- DDS Principle Introduction (Chinese) DDS direct digital frequency synthesizer, the principle and system design to achieve
s3esk_rotary_encoder_interface
- Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Ro
RGBtoYCbCr
- 采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件. -FPGA realization of the use of color space conversion RGB to Y CbCr of VHDL and Verilog source code, to support a variety of Xilinx devices.
pong
- Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of the Xilinx\Digilent Spartan-3 demo board.
cross_street_lights
- Cross street lights driver in VHDL. It have been tested on XILINX 9500.
OpenCorespcicore
- PCI IP核功能实现，符合V2.2协议-realize pci function
__FPGA_Prototyping_by_VHDL_Examples
- 在赛灵斯上用VHDL实现，串口，PS MOUSE, PS KEYBOARD..... 协议-on Xilinx,to achieve using VHDL too fullfill UART, PS MOUSE, PS KEYBOARD ..... prototype