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VHDL_simple_settable_clock
- 基于Xilinx ISE软件的用VHDL编写的一个简易的可调节时钟，具有时、分、秒功能-Xilinx ISE based,a simple settable clock using VHDL, with hours, minutes, seconds functions
suma_binaria7SEG
- binary adder on vhdl tested on xboard xilinx-binary adder on vhdl tested on xboard xilinx
bcd_to_7segmentos
- bcd to 7 segments display tested on xboard xilinx, all code developed on vhdl
4bits_adder
- 4 bit adder writen in vhdl with simulation, schematic and tested on x board xilinx
clock
- XPS做时钟的配置过程基于EXCD-1开发板,其实是基于xilinx的ISE来开发的，但是开发环境没有这个就这能选VHDL，另外是verilog的，呵呵。希望大家能够真正用上，挺好的“基于ISE的时钟”-XPS to do the configuration process is based on the clock EXCD-1 development board, in fact, is based on the xilinx the ISE to develop, but not the
xapp205_fifo_ctl
- XAPP205 Xilinx FIFO Controller VHDL code
XILINX_LABZ
- Xilinx labs which help in creating VHDL files for beginners.
test01
- 利用状态机编写的流水灯的VHDL程序源代码，基于xilinx公司的spartan3E入门级开发板。-Water prepared by a state machine VHDL source code lights, based on the company s spartan3E xilinx entry-level development board.
example9
- xilinx的ISE下，VHDL语言实现简单的vga显示红绿相间的条纹-xilinx under the ISE, VHDL language simple vga display red and green stripes
sram_simul
- Simple simulation example of SRAM in VHDL and Xilinx ISE
fulladder
- full adder code in vhdl using xilinx tool
lab5
- m*n的ram，包含m*n个ram，使用VHDL编译，可在xilinx里面运行-m* n the ram, contains m* n a ram, using the VHDL compiler, which can be run in xilinx
alu
- This 8 bit unsigned arithematic logical unit(ALU). This code is developed in VHDL language and compatible with any VHDL softeware like xilinx,quartus. This ALU performs addition,subtraction,multiplication,and,or,and not and pass input functions.-
T51
- Intel 8051 的民間版 VHDL 原始碼. 在 XILINX ISE 可合成並跑過.-One of the VHDL source code for MCU 8051. This source code was been verified and successful compiles on the XILINX ISE enviroment.
hello-world
- VHDL CODE FOR DISPLAYING " HAPPY WORLD " ON XILINX SPARTAN 3 E FPGA BOARD
seccount
- 用VHDL语言设计电子数字秒表。包含相关文件及说明，用户可以在Xilinx ISE 环境下运行。-With VHDL language design digital stopwatch. Contains the corresponding code and all documents. Users can Xilinx ISE environment in operation
pinlvup
- 利用XILINX的SPARTAN-3A系列的XC3S200A的FPGA为载体，以VHDL为系统逻辑描述的表达方式，完成的数字频率计的设计。-SPARTAN-3A XILINX the use of the FPGA family XC3S200A to vector to the system Logic VHDL descr iption expressions, completed the design of Digital Frequency Meter.
I2C_control
- Xilinx提供的I2C控制器代码,Master/Slave全功能- Readme File for I2C Customer Pack Created: 7/8/99 ALS Revised: 11/4/99 ALS ******************************************************************************************************************************
INTERLEAVER
- 1/3,k=9的卷积码VHDL实现,在xilinx ise上仿真成功。-1/3, k = 9 convolutional code VHDL implementation of the simulation in the xilinx ise success.
ISE0108
- xilinx ise 使用简明手册 vhdl fpga -xilinx ise