搜索资源列表
VHD
- 此为基于Xilinx的FPGA用VHDL实现的FIFO，已调通，可直接运行。-This is based on Xilinx FPGA using VHDL implementation of the FIFO, has been transferred through, can be directly run.
adcterbaru
- VHDL code for ADC Xilinx Spartan 3E
decoder
- It is a simple decoder created using vhdl in xilinx ise.It will helpful for beginners to create deocder using this.testbench for simulation is also created.
digital-storage-oscilloscope
- 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形-The problem to design a digital storage oscilloscope, to Xilinx, Inc. 200,000 FPGA chip as the core, supplemented by the necessary peripherals (incl
shuzidianyabiao
- 系统基于EDA技术的智能数字电压表实现,以现场可编程门阵列(FPGA)为设计核心，集成于一片Xilinx公司的SpartanⅡE系列XC2S100E-6PQ208芯片上，在ISE环境下采用超高速硬件描述语言(VHDL)模块化编程,实现了电压的数据采集、转换、处理、显示等功能。本设计的特点在于能够测量的电压范围宽（0~50VDC），主要采用了分压原理,该系统具有集成度高、灵活性强、易于开发和维护等特点。-System based on EDA technology of intelligent d
usb2.0 fpga
- 免费的USB2.0源码(支持Xilinx和Alteral的FPGA),用vhdl语言实现。-Free USB2.0 source (supports Xilinx and Alteral the FPGA), using vhdl language.
Using-JTAG-PROMs-for-data-storage
- Xilinx FPGA的配置中，从Flash中读写用户数据，包括VHDL、Verilog程序-in configuring Xilinx FPGA,reading and writing user data from flash,including the VHDL and Verilog code
PoE_2temac_TOP
- 基于xilinx公司生产的FPGA可编程逻辑芯片的千兆网卡的设计代码。-1000Mhz Ethernet TEMAC xilinx fpga vhdl RTL
xilinix-code-running-procedure
- this book useful ,how to run the vhdl code in xilinx 9.2i
uart1
- vhdl uart module. this file is used to transfer programs frm fpga xilinx spartam 3e kit to desktop pc through rs232 serial port.
61i_dp_bram_v5_0_vhdl_ise
- BRAM IN VHDL+ISE Xilinx
61i_dp_distram_v6_0_vhdl
- DISTRAM IN VHDL+ ISE Xilinx
xapp855
- FOR XILINX FPGA VHDL PROGRAMMING LVDS INTERFACE DEscr iptION
Ultra-9-17
- 超声波流量计采样控制部分的VHDL源代码，基于xilinx的spartan3-The ultrasonic flowmeter sampling control part of the VHDL source code, based on xilinx s spartan3
SHIFT-ROTATE
- Shift and Rotate VHDL code for Xilinx Spartan 3E board
ControlUnit
- Control Unit VHDL code. Xilinx Spartan 3E board
ClockGen
- ClockGen code in VHDL for Xilinx Spartan 3E board
spartan3e_hdl
- xilinx公司开发板内部集成单元模块功能介绍以及VHDL，Verilog实现。-xilinx development board internal integrated unit module functional descr iption and VHDL, Verilog implementation.
Package
- Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 11
dec
- sumador en vhdl, plataforma xilinx