搜索资源列表
uart_rx
- 用VHDL语言实现的Uart串口通信程序。在xilinx公司FPGA芯片验证过。-Uart serial communication program using VHDL. Validation in xilinx Company FPGA chip.
S16_ADC
- 基于xilinx的vhdl采集程序，芯片为AD7923-Based on the xilinx vhdl collection procedures chip AD7923
edge_detect
- 采用VHDL语言编写的边缘检测源代码，在xilinx公司的spatan-3an的仿真版上验证无误，供初学者学习-Edge detection using VHDL language source code, verification, simulation version of the company spatan-3an xilinx for beginners to learn
delight22
- 速度监控器，按键切换速度，数码管显示，若快到临界速度则闪烁。ISE，Xilinx，VHDL-The speed monitor, the key switching speed, digital display flashes if approaching the critical speed. ISE, Xilinx, VHDL
TAXI_TOLL_1_1
- 实现出租车自动计费器 能进行LCD1602液晶显示。硬件平台：Xilinx Spartan3E -Use VHDL languange to achieve the automatic taxi meter and display cost,waiting time and distance on the LCD1602 . Hardware platforms: Xilinx Spartan3E
Plasma_Cpu_r10.tar
- Plasma CPU: VGA coded with C and VHDL in Xilinx FPGA
pwm_lights
- 这是一个利用脉冲信号点亮LED灯的VHDL代码示例，可以用在xilinx的FPGA上-VHDL code example, a pulse signal lights LED lights can be used in the FPGA on xilinx
xapp1015
- SDI接口的VHDL实现，XILINX官网的设计参考-SDI interface VHDL realize XILINX official website design reference
Xilinx_vga_games_design
- 经典的程序，用VHDL编写的游戏，俄罗斯方块，在赛灵思Spartan板子上测试成功-Classic procedures, written in VHDL game, Tetris, on the board of the Xilinx Spartan test
XS3S1000
- XILINX公司XC3S1000FGG456下的VHDL工程,主要完成AD采用以及和CPU的数据交换-XC3S1000FGG456 s program example
8-3-Encoder
- VHDL program for “8:3 Encoder” behavioral design in Xilinx integrated software environment
BCD-ENCODER
- VHDL program for “Decimal To BCD Encoder” behavioral design in Xilinx integrated software environment
BIN-ENCODER
- VHDL program for “Octal To Binary Encoder” behavioral design in Xilinx integrated software environment
N---Bit-Full-SUBSTRUCTURE
- VHDL program for “N Bit Substructure” behavioral design in Xilinx integrated software environment
PARITY-ENCODER
- VHDL program for “Parity Encoder” behavioral design in Xilinx integrated software environment
shuzibiao
- xilinx下使用vhdl编写数字表 具有启动、复位、暂停、暂停后继续计时等功能 能显示的秒计数时间精确到小数点后第二位，即能显示**.**s -xilinx vhdl prepared using digital watch with a start, reset, pause, pause, continue after the timer function can display the seconds counting time accurate to the second
proj1
- 在Xilinx的ISE下用VHDL实现的3-8线译码器。-In the Xilinx ISE implementation using VHDL 3-8 line decoder.
13.Anvyl_PmodAD1_Demo
- 用VHDL写的AD程序，使用与xilinx开发板。-Written using VHDL AD process, use and xilinx development board.
14.Anvyl_PmodDA2_Demo
- 用VHDL写的da程序，使用与xilinx开发板。-Da program written using VHDL, use and xilinx development board.
06.Anvyl_vga_Demo
- 用VHDL写的VGA程序，使用与xilinx开发板。-Written using VHDL VGA procedures, using xilinx development board.