搜索资源列表
mips_project
- 我用verilog写的risc指令集的mips的cpu。可以支持定点运算。顶层单元是top。-I used to write verilog mips risc instruction set of the cpu. To support fixed-point arithmetic. Top-level unit is the top.
Chapter10
- 第十章的代码。 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
Openrisc1200
- 开源CPU核OpenRisc1200软核Verilog代码,学习CPU首选软核-OpenRisc
pic10_verilog
- 用verilog实现了PIC10系列单片机的IP核,代码基本来自一篇国外的文章《A Microchip PIC-Compatible RISC CPU IP Core Design and Verilog Implementation》,对一部分进行了改进,主要包括对原文中有一些不可综合的@(posedge clk)语句的改写,使其能通过quartus的编译和综合,并且对跳转部分增加了比较多的注释,这篇文章写得非常好,感谢这篇文章的作者John Gulbrandsen先生,这篇文章让我学到了很多
risc
- 基于quartus II软件 用verilog 语言描述的精简指令CPU-quartus II verilog
risc8_tar
- 用Verilog HDL完整的写出了cpu -Using Verilog HDL to write a complete cpu
CPU_code
- 基本的cpu verilog code 可用來瞭解基本cpu運作-Basic cpu verilog code can be used to understand the operation of the basic cpu
S7_PS2_RS232
- 利用cpld作为cpu控制器将ps2中取得按键值通过串口传送给pc机-cpld verilog ps2 UART
CPU_1
- 此文件为cpu的verilog学习代码,从最简单的cpu开始学习-This file is cpu to study the verilog code, from the simplest cpu to start learning
OR1200
- 用verilog编写的cpu,有点难度,大家慢慢看吧-Using verilog written cpu, a bit more difficult, we take your time
VerilogCPU
- Verilog设计CPU这是某一本书的PDF版。-Verilog design of CPU which is a book of the PDF version.
multi_cpu
- 多周期CPU,mips指令集,实现了部分指令,包含测试程序,verilog-Multi-cycle CPU
multi_cpu
- 使用Verilog语言编写的多周期CPU,能实现CPU24条指令,-Using the Verilog language multi-cycle CPU, can achieve CPU24 instructions,
SinglePeriodCPU
- verilog语言书写,单周期CPU源码-single period CPU
fivevhdl
- 5中cpu的程序,包含arm4,arm6,arm7等程序,的verilog实现-5 cpu procedures, including arm4, arm6, arm7 and other procedures, the verilog implementation
MultiCLKCPU
- 本设计实现了多周期CPU的设计,运行环境是quatrus2;该多周期CPU可以处理22条32位指令(具体指令见源码,绝不坑人)。压缩包内含有源代码,程序模块表和实验报告以及详细的设计图,是学习verilog的好材料啊。-The Design and Implementation of a multi-cycle CPU design, operating environment is quatrus2 the multi-cycle CPU can handle 22 32 instructi
071221088
- 实现一个简单的单周期流水线CPU,使用verilog语言开发 在quartus平台下运行-Implement a simple single-cycle pipelined CPU, using verilog language development platform running in quartus
061110061
- 在quartus平台下使用verilog语言编程实现简单的单流水线CPU,可以执行16条基本指令-Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions
cpu8
- 用Verilog仿真8条基本指令的CPU,是学习编写多条指令CPU的基础-Verilog simulation with the basic instructions 8 CPU, CPU to learn the basis for the preparation of multiple instructions
PipelinedCPU
- 用Verilog语言实现的流水线CPU设计,大家可以参考一下。-Using Verilog design language of the line CPU, you can reference.