搜索资源列表
lfsr
- 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
electric-8.08
- The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including: * Custom IC layout * Schematic Capture (digital and analog) * Textual Languages such a
subtracter_4
- 好还是verilog，现在你记忆可以，是关于FPGA的设计-Good or verilog, now you can remember, is the design on the FPGA
netfpga_full_3_0_1.tar
- NetFPGA开发基础包，里面有相关的实例工程，也有相关的源码，verilog HDL，C，JAVA等-NetFPGA development base package, there are examples of related works, there are also relevant source, verilog HDL, C, JAVA, etc.
Java--8268192Verilog--9726PLANER-41
- 拿出我心爱的源码Java 8268192Verilog 9726PLANER-41与给我同学一起分享，个人认为很不错的-Get out my beloved source Java planer 8268192 verilog- 9726-41 and to share with my classmate, personally think that good
LFSRTestbench
- java applet for dveleoping verilog code for lfsr
ecrvvtre 帮助文档
- dads 单位读卡器，为初学者提供遍历的Java原代码，仅供参考(adssdcwenoefoir,kvriubtkcmnrjascerfvvbwkcb)