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AVR8 cpu的verilog 源码 欢迎下载使用
AVR8 cpu的verilog 源码 欢迎下载使用-AVR8 cpu s verilog welcome to download source code verilog using AVR8 cpu s welcome to download AVR8 cpu welcome to download the source code verilog
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交通信号灯的verilog实现,里面包含有源程序和仿真图。-Verilog realize traffic lights, which contains the source code and simulation diagram.
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蓝牙协议v2.0加解密和认证算法的实现,其中包括C++源代码,以及设计文档和相关参考资料,以及硬件实现的verilog代码。-Bluetooth protocol v2.0 encryption and authentication algorithm, which includes C++ source code, and design documents and related reference materials, and hardware implementation verilog
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vhdL还有fpga和verilog非常有用的嵌入式串并的源代码-vhdL also very useful verilog fpga and embedded string and source code
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同步FIFO源代码,使用Verilog编写,用户可以轻松转换成VHDL。-Synchronized FIFO source code
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国外权威著作-数字信号处理的FPGA实现(第三版)的源代码,包括VHDL和verilog两种格式。-Foreign authoritative writings- digital signal processing on FPGA (third edition) of the source code, including VHDL and verilog formats.
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pci 32位33M的从设备接口的实现源代码,使用verilog语言设计的,对设计自己的pci软核很有参考价值。-pci 32 位 33M slave device interface source code, using verilog language design, the design of their pci soft core of great reference value.
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硬件描述语言设计的串口发送源代码UART TX SOURCE CODE-Verilog HDL UART TX RTL SOURCE CODE
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altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
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基于Verilog HDL FPGA开发,时序篇详细教程代码,丰富实例源代码,FPGA学习与参考非常好用-Based on Verilog HDL FPGA development, timing articles detailed tutorial code, abundant source code examples, FPGA is very useful learning and reference
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FPGA的IP核中除法算法的源代码,是Verilog语言的,易于初学者的学习。-FPGA IP core in the division algorithm source code, Verilog language, easy for beginners to learn.
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verilog 语言写的交通灯设计源代码,实现左转灯、红灯、绿灯、黄灯转换,并且提供手动控制按钮-verilog language source code for design of traffic lights, turn left to achieve lights, red light, green light, yellow light conversion, and provides manual control buttons
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本压缩包,包换一个用verilog语言实现的huffman编码源程序,同时给出了众多论文和基础知识的文档资料,一应俱全。-The compression package, shifting one using huffman coding verilog language source code, and gives basic knowledge of many papers and documentation, everything.
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本例程位于 VMD642_CPLD目录中。
使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使
用 Verilog HDL书写,编译开发系统使用 Cypress公司的 Warp 6.3。-This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and othe
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TI C6474评估板的fpga源代码,初始化板子必备代码,Verilog HDL硬件语言编写。-TI C6474 evaluation board fpga source code, the code necessary to initialize the board, Verilog HDL hardware language.
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Verilog/VHDL源码的串口示例,“Altera设计基础篇”第3章的串口示例,包括源码和仿真文件等-Verilog/VHDL source serial example, " Altera Design Basics" in Chapter 3 serial examples, including source code and simulation files, etc.
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Xlink应用例子关于UART的Verilog实现的源代码-Xlink application examples about UART Verilog realization of the source code
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uart接口verilog源码,实现数据串并行的转换。内容包含十个代码文件。-uart Interface verilog source of data for serial-parallel conversion. Contains ten code files.
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基于verilog的三速以太网源程序,文件中包含源程序和测试程序。-tri_model ethernet source code based on vhdl languange, include source code and testbench in the file.
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eDP接口TFT-LCD显示驱动原码(verilog+c)-eDP Interface TFT-LCD display driver source code (verilog+c)
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