搜索资源列表
FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
verilog-program
- 国外经典verilog程序集锦，含有从最简单的定时器创建到复杂逻辑的实现。-Classic Collection verilog program abroad, with the timer created from the most simple to complex logic.
gh_timer_8254_081608
- Timer 8254 Verilog source code
FPGA_jiaocheng_yu_shiyan
- 最重要的是七个从简单到复杂的实验，包括：基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真 基础实验三_SOPC_LED 基础实验四_Flash烧写 基础实验五_定时器实验 基础实验六_按键以及PIO口中断实验 实验七_网卡使用 ，这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写，有实验板和没有实验板的都可以用来学习。 其次还包括： FPGA开发板各存储器之间的联系、 多处理器文档 、 USB_UART等文档，很好用的文档，您下了相信不会后悔！-
timer
- 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
Timer
- ep2c5 实现 定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
pit_latest.tar
- Programmable Interval Timer: Overview Category :: Other Language :: Verilog Development status :: Beta WishBone Compliant :: Yes Phazes :: Design done, Specification done
timeclock
- 基于verilog的时钟定时器的硬件实现，可以实现时钟定时报时功能-Based on the verilog hardware timer clock can be achieved from time to time time clock function
jishu60
- verilog实例，用verilog模块例化方式设计一个60S的定时器。-verilog example verilog modules were used to design a way of timer 60S.
timer
- 计时器的Verilog描述 CPU设计者可以借鉴 -Verilog decription of the timer in processors
StopWatch
- 用C#写的跑表，用于学习Timer控件和C#下的stopwatch类，在VS.net 2005下运行通过.-Using C# to write the stopwatch for the study and Timer controls and C# under the stopwatch class, VS.net 2005 in the run through.
watch_dog_rtl_source
- Watchdog timer verilog RTL code
timer_rtl_source
- Timer verilog RTL code
verilog
- verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signal
mytime
- Verilog实现的实时时钟 功能，时分秒-Verilog timer
LIP1701CORE_system_watchdog
- System watchdog verilog code
verilog
- Verilog HDL 1.红外线发射调制电路 2.分数分频 3.最大公约数和最小公倍数 4.秒表-1.infra transmission modulator 2.fractal frequency divider 3.maximal common divisor 4.timer
DW8051_core
- 8051的内核源码,用verilog HDL写成，已验证功能正确-open core fo 8051 cpu
time-counter
- 基于verilog的计时器源代码，可以通过编译-Verilog source code based on the timer, you can compile
timer0
- 一个简单的timer，包括定时器，计数器功能模式，非常实用，供参考(A simple timer, including timer, counter function mode, very practical, for reference.)