搜索资源列表
Tetris-VHDL
- 利用FPGA和VGA显示器实现的俄罗斯方块游戏。 使用VHDL语言和Xilinx开发。-Using FPGA and VGA monitor to develop a Tetris game. Developed using VHDL language and Xilinx .
module-song2
- xilinx VERILOG fpga BASYS2 音乐单次播放实现-xilinx VERILOG fpga BASYS2 music single player to achieve
11-songer
- 基于Xilinx Spartan6的FPGA案例 播放 梁祝 的程序 VHDL-Play Lovers of FPGA-based Xilinx Spartan6 case program VHDL
RS_Encode_Decode
- RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。-RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.
mb
- xilinx公司Microblaze核源文件，版本v7_10_a，语言VHDL，用于FPGA开发和DC综合-xilinx company Microblaze nuclear source file, version v7_10_a, language VHDL, and FPGA development for integrated DC
HDMI_test
- 基于Xilinx的FPGA的spartan3的HDMI测试功能刷屏显示。-Based on Xilinx s FPGA spartan 3e of the HDMI display refresh function tests.
kc724-schematic
- Xilinx Kintex-7，Xilinx Kintex-7 FPGA KC724 特性描述套件，硬件原理图-Xilinx Kintex-7
DSSS
- 用VHDL实现基于Xilinx的FPGA上的直接序列扩频通信，并且附带了matlab仿真程序。-VHDL implementation based on direct sequence spread spectrum communication on Xilinx' s FPGA, and comes with matlab simulation program.
DEMUX1_4
- this project about demultiplexer one to four compiled and implanted in cart fpga xilinx 3E, with file .bit
MUX4_1_2bits_fonction
- this project about multiplexer four to one compiled and implanted in cart fpga xilinx 3E, with file .bit
m_counter
- this project about compteur m bit compiled and implanted in cart fpga xilinx 3E, with file .HDL and .bit
Tetris_Zedboard
- 俄罗斯方块 ”FPGA实现本项目主要在FPGA上实现了一个经典小游戏“俄罗斯方块”。本项目基本解决方案是，使用Xilinx Zynq系列开发板ZedBoard作为平台，实现主控模块，通过VGA接口来控制屏幕进行显示。-New Tetris
ug195
- 这个文档是关于xilinx virtex-5 FPGA板的封装和管脚定义文件，对于使用v5 有很大的帮助-This document is package and pin definitions files about xilinx virtex-5 FPGA board for use v5 great help
my_spi_done
- Xilinx EDK开发 通过FPGA实现SPI通信-DK Xilinx development through SPI to achieve FPGA communication
uartsample
- Xilinx EDK开发 通过FPGA实现UART通信-EDK Xilinx development through FPGA to achieve UART communication
Sparten6-CODE-_Verilog
- 基于xilinx 厂商的FPGA硬件的开发源代码，包括UART,SPI,以太网通信-The development of FPGA hardware based on xilinx manufacturers source code, including the UART, SPI, Ethernet communication and so on
shatest_xapp780_fix_bug
- 操作DS2432 1-Wire芯片进行数据读写，加密解密的FPGA源代码，基于xilinx xapp780并进行改进.在Spartan3 XC3S400上测试通过.使用ISE14.7打开proect shatest.xise. 内附源代码和相关开发手册。对于在FPGA上利用DS2432加密的开发非常实用。-Used to test the DS2432 1-Wire encryption function. Tested on Spartan3 XC3S400.
viterbi_soft
- 维特比译码器，调用IP核，软判决输入，开发平台Xilinx Spartan-6系列FPGA-viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA
turbo_code
- LTE system, OFDM modulation and Turbo Coding, including Viterbi, BCJR and SOVA are extensively analysed, ending up with a system performance specification. These are used to implement a fixed length Turbo encoder, a 16-QAM modulator a
turbo_lte_ofdm_fpga_code
- LTE system, OFDM modulation and Turbo Coding, including Viterbi, BCJR and SOVA are extensively analysed, ending up with a system performance specification. These are used to implement a fixed length Turbo encoder, a 16-QAM modulator a