搜索资源列表
finalTURBOCODE_OFDM
- Throughout the project the LTE system, OFDM modulation and Turbo Coding, including Viterbi, BCJR and SOVA are extensively analysed, ending up with a system performance specification. These are used to implement a fixed length Turbo enco
adc_dac
- ADC-DAC transmittion works thru SPI on 25 MHZ. Used for some student project on Xilinx sprtan3a FPGA
work
- fpga实现iic通信功能,bh1750 xilinx spartan3-iic fpga
nexys4-ddr_sw_demo
- The Nexys4 DDR board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) Xilinx® . With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C)
VGA-controller
- VGA controller tested on Xilinx Spartan 6 FPGA on Nexys 3 board
xapp1178
- Source code for xilinx dp application for fpga
wiznet5500_Verilog
- 使用Xilinx Spartan-6 XC6SLX9的FPGA驱动Wiznet5500网卡芯片的Verilog设计，可以发送和接收，已经测试，无误。-Using the Xilinx Spartan-6 XC6SLX9 FPGA driver The Wiznet5500 network card chip Verilog design can be sent and received, has been tested, and is correct.
wkether
- xilinx virtex fpga 这是一个用来检测局域网是否正常的程序的源代码-Xilinx virtex fpga whether this is a used to detect local area network (LAN) normal program source code
nttwork
- xilinx virtex fpga 这是一个用来检测局域网是否正常的程序的源代码-Xilinx virtex fpga whether this is a used to detect local area network (LAN) normal program source code
Implement-a-CPU
- 在FPGA赛灵思基础3上使用Verilog HDL实现支持MIPS操作子集的CPU-Implement a CPU which supports a subset of MIPS operations using Verilog HDL on FPGA Xilinx Basys 3
ukwvf
- xilinx virtex fpga 这是一个用来检测局域网是否正常的程序的源代码(Xilinx virtex fpga whether this is a used to detect local area network (LAN) normal program source code)
ALTERA
- we are in this file about altera fpga xilinx communication syaterm toolbox for design and system requirements
h265enc_v1.0
- 用vhdl语言编写的h.265编码器，可用于xilinx或altera的fpga(h.265 encoder written by vhdl. It can be download to xilinx or altera's fpga)
UART-HPY
- 利用FPGA实现了UART编解码功能，已在Xilinx及Altera多种型号FPGA例化使用。附有寄存器使用说明。(a useful UART decoder and encoder.)
Verilog HDL program
- 文件详细讲述了使用XILINX产FPGA在ISE平台开发的方法，介绍了Modelsim，chipscope,textbench等仿真方法，并含大量实例以及源代码(File details on the use of XILINX produced FPGA in the ISE platform development methods, introduced the Modelsim, chipscope, textbench and other simulation methods, and
黑金Sparten6开发板Verilog教程V1.6
- 黑金xilinx ise fpga verlog 教程(Black gold Xilinx, ise, FPGA, verlog tutorials)
VGA
- vga code for fpga 3s500e spartan xilinx code verilog tutorial video graphics array in verilog interfacing with fpga xilins spattan 3e very easy to learn
FSK
- 首先利用IP核记录sin和con波形，然后进行FSK调制，信息为数字信息(Firstly, the IP kernel is used to record the sin and con waveforms, and then the FSK is modulated, and the information is digital information)
mig_7series_0_ex
- 嵌入式 单片机编程 内存控制器 赛灵思 使用教程(fpga mig xilinx Embedded microcontroller programming memory controller Xilinx tutorial)
pll_test
- PLL，即锁相环。是FPGA中的重要资源。由于一个复杂的FPGA系统往往需要多个不同频率，相位的时钟信号。所以，一个FPGA芯片中PLL的数量是衡量FPGA芯片能力的重要指标。FPGA的设计中，时钟系统的FPGA高速的设计极其重要，一个低抖动, 低延迟的系统时钟会增加FPGA设计的成功率。本例程调用Xilinx提供的PLL核来产生不同频率的时钟, 并把其中的一个时钟输出到FPGA外部IO上, 也就是开发板的SMA接口上。(PLL, pll. It's an important resource