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AES256-XILINX10.1
- 用XILINX公司提供的NetFPGA板卡并结合软件Xilinx10.1进行系统设计，采用硬件描述语言Verilog实现了 AES-256加密算法。-Provided by XILINX board combined with software Xilinx10.1 NetFPGA system design, using Verilog hardware descr iption language implementation of the AES-256 encryption algorit
63535312DCTofJPEG
- 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
aes
- 其程序是用xilinx环境下编写的，风格是Verilog，请大家提意见。-The program is written using xilinx environment, style Verilog, please comments.
subbyte128
- AES算法中Sbox映射Verilog源代码，采用一一映射的方案，用查找表的方式实现Sbox。转换数据长度为128bit。-Sbox mapping Verilog source code of the AES algorithm, using one to one mapping of the program, using a lookup table to achieve the Sbox table. Convert the data length is 128bit.
AES-based-on-FPGA-jiemi
- 基于FPGA的AES算法实现，使用verilog语言实现。本模块只包含解密过程，没有加密过程。-Implementation of AES algorithm based on FPGA, using Verilog language. This module contains only the decryption process, no encryption process.
tiny_aes_latest.tar
- 主要实现使用verilog HDL语言实现AES的加密算法-Main implementation using verilog HDL language implementation of AES encryption algorithm
aes__code_based_on_verilog
- AES核心代码，用verilog写的，可供参考-aes core code using verilog for learning
基于FPGA的AES256位加密
- aes 256位 算法 加密程序，使用verilog 语言(AES 256 bit algorithm encryption program, using Verilog language)