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CODE.rar
- AHB总线下的slave ram的verilog代码,AHB bus slave ram verilog
AHB-BUS-AND-SLAVE-CODE-USING-VERILOG
- AHB总线下的slave代码verilog-AHB BUS AND SLAVE CODE USING VERILOG
AHB_slave-ram
- AHB总线下的slave ram的verilog代码-AHB bus slave ram under the verilog code
ACODEH
- AHB总线下的slave ramm的verilog代码 -Verilog code of the AHB bus slave ramm
ahb_slave
- AHB SLave code in verilog
ahb_slave
- 异步memory ahb lite slave接口verilog代码-verilog code of ahb lite slave for memory interface
slave_ahb1988
- slave ahb 1988 verilog
verilog
- AHB BUS, Master Slave Arbiter,AHB System是由Master，Slave，Infrastructure 三部分所组成。-example-AHB BUS, Master Slave Arbiter
ahb
- verilog实现AHB总线上的主从控制，在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)
AHB2-master
- verilog ahb master and slave