搜索资源列表
VerilogCode_8-bit_2to1_mux
- Verilog Code for 8 to 1 multiplexer for the code to be implemented on Altera DE2 board
VerilogCode_BCD_counter
- Verilog Code for a BCD counter and it is implemented on Altera DE2 board-Verilog Code for a BCD counter and it is implemented on Altera DE2 board
DE2_Web_Server
- 此文件是altera公司发布的基于DE2开发板的-web例程，能实现DE2开发板与计算机之间的信息传输，采用vhdL语言编写。-This file is Announces altera DE2 development board based on the-web routine, to achieve DE2 development board and the transfer of information between computers, using vhdL language.
CONTROL_DAC
- Seno Generator, for Altera DE2-70 This is a generator of seno signal and the output will be displayed in the VGA DAC of the board
Promediador
- This a Promediator for the Altera DE2-2 it use a looktable for obtein the data and then promediates the current sample with 3 past samples.-This is a Promediator for the Altera DE2-2 it use a looktable for obtein the data and then promediates the cur
tutorial
- another verilog VHDL tutorial, targeting altera DE2 board, but very intuituve.
DE2_Default
- Altera DE2 demonstration design, lot of interesting verilog code for synthesis
DE2_70_demonstrations_V10
- altera公司的de2板子的一些资料和例子。学习fpga开发板的需要这个-altera de2 board some of the company' s information and examples. Fpga development board to learn the needs of the
5-multiplexer
- five multiplexer, verilog, altera de2 board~
Rapid_Prototyping_of_Digital_Systems__SOPC.tar
- Rapid prototyping of Digital system and SOPC VHDL Altera DE2 board
AnalizatorAndCounter
- VHDL counter project fo Altera DE2 Development Board-VHDL counter project fo Altera DE2 Development Board
TestSpeed
- test aplication for Altera DE2 development board
DE2_CCD_detect
- de2,altera fpga开发板，自带的源码，ccd_detect-de2, altera fpga development board, comes with source code, ccd_detect
Embeddedp20Systemsp20Laboratoryp20Exercisep204p20
- DE2_NET Tutorial. A descr iption and steps to execute a example of the ethernet controller of DE2 board - Altera.
DE2_USB_API
- altera d2e usb api example
part1
- ALTERA DE2-115 LAB EXC. PART1 CODE
nios2audio
- 通过altera开发板DE2_70实现语音记录与播放，添加FIR滤波器提升语音质量。附加硬件功能方框图以及软件流程图，以及改进方法。-By altera board DE2_70 voice recording and playback, added FIR filter to enhance the voice quality. Additional functional block diagram of the hardware and software flow chart, as wel
based-DE2-jpeg-encoder-design
- 使用基于Altera公司的DE2平台进行JPEG 编码器的设计与实现，硕士论文-Altera' s DE2-based platform for JPEG Encoder Design and Implementation, Master' s thesis
tv_csync_gen
- Generator of composite synchronisation TV signal on Altera DE2-35 board.
part1
- Altera DE2 开发板试验2 第1部分VHDL答案-Altera DE2 Lab2 part1 VHDL answer