搜索资源列表
APB
- It s the verilog source code for AMBA APB 2.0 Slave
RTC
- verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等-verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other
eth
- 一个ahb接口的千兆以太网MAC，包括apb的配置接口-Ahb a Gigabit Ethernet interface MAC, including the configuration interface apb
lab1
- apb transactions with DUT, testbench including interface test cases , top
SOC
- SOC AMBA 总线接口代码，适合了解AHB APB协议-SOC AMBA bus interface code for understanding AHB APB protocol
interrupt_controller
- 中断控制器电路verilog实现源代码,silicon验证的.-interrupt controller IP source code, APB interface.
apbtoaes128_latest.tar
- AES加密算法verilog代码实现，基于APB总线接口数字IP，包含详细的testbench-AES encryption algorithm verilog code, based on the APB bus interface digital IP, contains a detailed testbench
apbi2c_latest.tar
- APB总线协议转I2C总线协议的接口IP，verilog代码实现，包含详细testbench-APB bus interface to I2C bus interface IP，verilog code
apb_spi
- Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface
timer
- Simple 32-bit timer realization with APB interface with support of interrupt generation and switching clock source.
Ahb2Apb
- AHB总线协议转APB总线协议的接口IP，使用Verilog代码实现，有详细的英文注释(AHB bus protocol turn APB bus interface IP, use Verilog code implementation, and have a detailed knowledge of the English comments)
apb_uart
- 带apb接口的uart,带testbench，测试过，可以使用(The uart module with apb interface)
apb_uart_sv-pulpinov1
- SystemVerilog 写的APB总线接口的uart 代码，带testbench.(Uart code of APB bus interface written by SystemVerilog, with testbench.)
24_Timer
- 使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
AXI&APB2SPI
- APB总线转SPI接口模块SV代码以及AXI总线转SPI接口模块SV代码(SV code of APB bus to SPI interface module and SV code of Axi bus to SPI interface module)
apbi2c-master
- apb转i2c verilog 实现(APB bus interface to I2C bus interface)