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verilog-arbiter.tar
- Verilog arbitrator for Wishbone R3 compliant bus
Router
- 5 Pin Router with Virtual Output Queues 32 bit arbiter optional encoder and decoder also included along with priority encoder-5 Pin Router with Virtual Output Queues 32 bit arbiter optional encoder and decoder also included along with priority encode
mpc6xx
- Worker thread to service arbiter mappings based on dev SKUs.
brcm-gisb-arb
- Broadcom GISB bus Arbiter controller.
vgaarbiter
- To use the vga arbiter char device it was implemented an API inside the libpciaccess library.
spmi-pmic-arb
- PMIC Arbiter configuration registers.
qcom-spmi-pmic-arb
- Qualcomm SPMI Controller (PMIC Arbiter).
ahb
- 基于AMBA2.0的AHB 总线，包括arbiter，decoder，Muxs2m,Muxm2s-Based AMBA2.0 the AHB bus, including the arbiter, decoder, Muxs2m, Muxm2s
shudianfangzhen
- 使用multisim设计的数电小实验 路灯控制电路 举重裁判表决器 开关报警电路-Use multisim design small number of electric street lighting control circuit weightlifting referee experiment arbiter switch alarm circuit
ArbiterRR
- Round Robin Arbiter vhdl
scalable_arbiter_latest.tar
- a scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speed with up to hundreds of request lines, and it grants in just a few clock cycles.
ahb_system_generator_latest.tar
- AHB system generator. This file is a part of a system generator for AHB system. it is VHDL code for the AMBA arbiter.
verilog
- AHB BUS, Master Slave Arbiter,AHB System是由Master，Slave，Infrastructure 三部分所组成。-example-AHB BUS, Master Slave Arbiter
AMBA
- AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型-AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave
round_robin
- Round Robin priority arbiter
dma_rtl
- 该代码实现了一个基于Wishbone总线协议的DMA控制器，由于SOC可集成的模块越来越多，本文设计的DMAC包含了31个可编程的DMA通道，能够处理多个DMA传输请求。由于数据在Wishbone总线上传输，在总线接口方面，本文设计的DMAC提供了两个既可以作为主机接口又可以作为从机接口的Wishbone接口。当有多个外设同时发出DMA请求时，本文设计的DMAC采用循环优先级和动态优先级相结合的方式，实现了通道仲裁器二级仲裁的功能。为了提高传输效率，本文设计的DMAC不仅支持数据块的传输，还支持
Weighted-Round-Robin-Arbiter-master
- 带权重的优先级轮转算法的verilog实现(Verilog implementation of priority rotation algorithm with weight)