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multi_booth
- verilog编写的booth算法的8x16乘法累加器-verilog prepared booth algorithm 8x16 multiplier-accumulator
BOOTH2
- verilog booh multiplier-booth
BOOTH2
- verilog booh multiplier-booth
SEQ_MULT
- SEQUENTIAL MULTIPLIER IN VERILOG USING BOOTH S ALGORITHM
booth_multiplie_module
- 利用verilog实现的Booth算法乘法器,对想学习乘法器的将会有很大的帮助.-Booth algorithm verilog realization use multipliers, the multiplier will want to learn a great help.
cmp42
- 用于乘法器设计,8位Booth译码乘法器,4-2压缩结构,加速乘法运算速度-Used for the design of multiplier, 8 Booth decoding multiplier, 4-2 compressed structure, accelerate the multiplication rate
15x15mul
- 自己写的布斯4算法的华莱士树无符号数乘法器,3-2压缩,亲测可用-Wallace wrote the number 4 Booth algorithm unsigned multiplier, 3-2 compression, pro-test available