在FPGA上实现BPSK信号的解调，全部用VHDL语言编写，非常实用。-Implemented on the FPGA BPSK signal demodulation, all with the VHDL language, very useful.

基于verilog HDL的BPSK解调的FPGA实现，仿真结果验证良好。IDE为vivado 2014( U57FA u4E8Everilog HDL u7684BPSK u89E3 u8C03 u7684FPGA u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u826F u597D u3002IDE u4E3Avivado 2014)